From 2121a45b69008f6465f48044c3d741a6cd047e57 Mon Sep 17 00:00:00 2001
From: James Talbert <jtalbert@iastate.edu>
Date: Mon, 15 Oct 2018 16:59:15 -0500
Subject: [PATCH] Created a new XSDK project for the new hawdware platform. The
code runs on the board, PWM is generated out (value unverified) but the I2C
sensors are not attached, so there code fails quickly after that.
---
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.../libsrc/standalone_v6_7}/src/xenv.h | 0
.../standalone_v6_7}/src/xenv_standalone.h | 0
.../libsrc/standalone_v6_7}/src/xil-crt0.S | 11 +-
.../libsrc/standalone_v6_7}/src/xil_assert.c | 0
.../libsrc/standalone_v6_7}/src/xil_assert.h | 0
.../libsrc/standalone_v6_7}/src/xil_cache.c | 36 +-
.../libsrc/standalone_v6_7}/src/xil_cache.h | 0
.../libsrc/standalone_v6_7}/src/xil_cache_l.h | 0
.../standalone_v6_7}/src/xil_cache_vxworks.h | 0
.../libsrc/standalone_v6_7/src}/xil_errata.h | 8 +-
.../standalone_v6_7}/src/xil_exception.c | 43 +-
.../standalone_v6_7/src}/xil_exception.h | 6 +-
.../libsrc/standalone_v6_7}/src/xil_hal.h | 0
.../libsrc/standalone_v6_7}/src/xil_io.c | 0
.../libsrc/standalone_v6_7/src}/xil_io.h | 4 +-
.../standalone_v6_7}/src/xil_macroback.h | 0
.../libsrc/standalone_v6_7}/src/xil_mem.c | 0
.../libsrc/standalone_v6_7}/src/xil_mem.h | 0
.../src/xil_misc_psreset_api.c | 0
.../src/xil_misc_psreset_api.h | 0
.../libsrc/standalone_v6_7}/src/xil_mmu.c | 0
.../libsrc/standalone_v6_7}/src/xil_mmu.h | 0
.../libsrc/standalone_v6_7}/src/xil_printf.c | 13 +-
.../libsrc/standalone_v6_7/src}/xil_printf.h | 4 +
.../standalone_v6_7/src/xil_sleepcommon.c} | 96 +-
.../standalone_v6_7/src/xil_sleeptimer.c | 162 +
.../standalone_v6_7/src/xil_sleeptimer.h | 116 +
.../standalone_v6_7}/src/xil_testcache.c | 0
.../standalone_v6_7}/src/xil_testcache.h | 0
.../libsrc/standalone_v6_7}/src/xil_testio.c | 0
.../libsrc/standalone_v6_7}/src/xil_testio.h | 0
.../libsrc/standalone_v6_7}/src/xil_testmem.c | 0
.../libsrc/standalone_v6_7}/src/xil_testmem.h | 0
.../libsrc/standalone_v6_7}/src/xil_types.h | 0
.../libsrc/standalone_v6_7}/src/xl2cc.h | 0
.../standalone_v6_7}/src/xl2cc_counter.c | 0
.../standalone_v6_7}/src/xl2cc_counter.h | 0
.../standalone_v6_7}/src/xparameters_ps.h | 7 +-
.../standalone_v6_7}/src/xplatform_info.c | 38 +-
.../standalone_v6_7}/src/xplatform_info.h | 16 +-
.../libsrc/standalone_v6_7}/src/xpm_counter.c | 0
.../libsrc/standalone_v6_7}/src/xpm_counter.h | 0
.../libsrc/standalone_v6_7}/src/xpseudo_asm.h | 0
.../standalone_v6_7/src}/xpseudo_asm_gcc.h | 7 +
.../standalone_v6_7}/src/xreg_cortexa9.h | 0
.../libsrc/standalone_v6_7}/src/xstatus.h | 0
.../libsrc/standalone_v6_7}/src/xtime_l.c | 0
.../libsrc/standalone_v6_7/src}/xtime_l.h | 13 +-
.../libsrc/uartps_v3_6}/src/Makefile | 0
.../libsrc/uartps_v3_6}/src/xuartps.c | 5 +-
.../libsrc/uartps_v3_6}/src/xuartps.h | 6 +-
.../libsrc/uartps_v3_6}/src/xuartps_g.c | 2 +-
.../libsrc/uartps_v3_6}/src/xuartps_hw.c | 2 +-
.../libsrc/uartps_v3_6/src}/xuartps_hw.h | 8 +-
.../libsrc/uartps_v3_6}/src/xuartps_intr.c | 2 +-
.../libsrc/uartps_v3_6}/src/xuartps_options.c | 2 +-
.../uartps_v3_6}/src/xuartps_selftest.c | 2 +-
.../libsrc/uartps_v3_6}/src/xuartps_sinit.c | 2 +-
.../libsrc/usbps_v2_4/src/Makefile | 0
.../libsrc/usbps_v2_4/src/xusbps.c | 2 +-
.../libsrc/usbps_v2_4/src}/xusbps.h | 4 +-
.../libsrc/usbps_v2_4/src/xusbps_endpoint.c | 2 +-
.../libsrc/usbps_v2_4/src}/xusbps_endpoint.h | 2 +-
.../libsrc/usbps_v2_4/src/xusbps_g.c | 2 +-
.../libsrc/usbps_v2_4/src/xusbps_hw.c | 2 +-
.../libsrc/usbps_v2_4/src/xusbps_hw.h | 2 +-
.../libsrc/usbps_v2_4/src/xusbps_intr.c | 2 +-
.../libsrc/usbps_v2_4/src/xusbps_sinit.c | 2 +-
.../libsrc/xadcps_v2_2/src/Makefile | 0
.../libsrc/xadcps_v2_2/src/xadcps.c | 0
.../libsrc/xadcps_v2_2/src}/xadcps.h | 4 +-
.../libsrc/xadcps_v2_2/src/xadcps_g.c | 2 +-
.../libsrc/xadcps_v2_2/src/xadcps_hw.h | 0
.../libsrc/xadcps_v2_2/src/xadcps_intr.c | 0
.../libsrc/xadcps_v2_2/src/xadcps_selftest.c | 0
.../libsrc/xadcps_v2_2/src/xadcps_sinit.c | 0
.../system_bsp/system.mss | 42 +-
410 files changed, 2216 insertions(+), 177969 deletions(-)
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delete mode 100644 quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/system.hdf
rename quad/xsdk_workspace_vivado/{recorder_test => real_quad}/src/Xilinx.spec (100%)
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delete mode 100644 quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo.c
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delete mode 100644 quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_global_timer.c
delete mode 100644 quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_gps.c
delete mode 100644 quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_i2c.c
delete mode 100644 quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_imu.c
delete mode 100644 quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_lidar.c
delete mode 100644 quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_mio7_led.c
delete mode 100644 quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_motor.c
delete mode 100644 quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_optical_flow.c
delete mode 100644 quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_rc_receiver.c
delete mode 100644 quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_system.c
delete mode 100644 quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_tests.c
delete mode 100644 quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_uart.c
delete mode 100644 quad/xsdk_workspace_vivado/real_quad_fresh/src/lscript.ld
delete mode 100644 quad/xsdk_workspace_vivado/real_quad_fresh/src/main.c
delete mode 100644 quad/xsdk_workspace_vivado/real_quad_fresh/src/platform.c
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delete mode 100644 quad/xsdk_workspace_vivado/real_quad_fresh/src/platform_config.h
delete mode 100644 quad/xsdk_workspace_vivado/recorder_test/.cproject
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delete mode 100644 quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/sleep.h
delete mode 100644 quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xttcps.h
delete mode 100644 quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xttcps_hw.h
delete mode 100644 quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/Makefile
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delete mode 100644 quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/Makefile
delete mode 100644 quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.c
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delete mode 100644 quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out_selftest.c
delete mode 100644 quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sleep.h
delete mode 100644 quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/Makefile
delete mode 100644 quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps.c
delete mode 100644 quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps.h
delete mode 100644 quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_g.c
delete mode 100644 quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_hw.h
delete mode 100644 quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_options.c
delete mode 100644 quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_selftest.c
delete mode 100644 quad/xsdk_workspace_vivado/standalone_bsp_0/system.mss
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/_profile_timer_hw.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/bspconfig.h (89%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/mblaze_nt_types.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/profile.h (100%)
rename quad/xsdk_workspace_vivado/{quad_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/src => system_bsp/ps7_cortexa9_0/include}/pwm_recorder.h (100%)
rename quad/xsdk_workspace_vivado/{quad_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/src => system_bsp/ps7_cortexa9_0/include}/pwm_signal_out.h (100%)
create mode 100644 quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/sleep.h
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/smc.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/vectors.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src => system_bsp/ps7_cortexa9_0/include}/xadcps.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xadcps_hw.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xbasic_types.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src => system_bsp/ps7_cortexa9_0/include}/xcoresightpsdcc.h (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_4/src => system_bsp/ps7_cortexa9_0/include}/xcpu_cortexa9.h (86%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/ddrps_v1_0/src => system_bsp/ps7_cortexa9_0/include}/xddrps.h (96%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xdebug.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src => system_bsp/ps7_cortexa9_0/include}/xdevcfg.h (97%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xdevcfg_hw.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xdmaps.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xdmaps_hw.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src => system_bsp/ps7_cortexa9_0/include}/xemacps.h (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src => system_bsp/ps7_cortexa9_0/include}/xemacps_bd.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src => system_bsp/ps7_cortexa9_0/include}/xemacps_bdring.h (97%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xemacps_hw.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xenv.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xenv_standalone.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src => system_bsp/ps7_cortexa9_0/include}/xgpio.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src => system_bsp/ps7_cortexa9_0/include}/xgpio_l.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src => system_bsp/ps7_cortexa9_0/include}/xgpiops.h (95%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xgpiops_hw.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xiicps.h (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src => system_bsp/ps7_cortexa9_0/include}/xiicps_hw.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xil_assert.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xil_cache.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xil_cache_l.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xil_cache_vxworks.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src => system_bsp/ps7_cortexa9_0/include}/xil_errata.h (96%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src => system_bsp/ps7_cortexa9_0/include}/xil_exception.h (97%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xil_hal.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src => system_bsp/ps7_cortexa9_0/include}/xil_io.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xil_macroback.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xil_mem.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xil_misc_psreset_api.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xil_mmu.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src => system_bsp/ps7_cortexa9_0/include}/xil_printf.h (91%)
create mode 100644 quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xil_testcache.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xil_testio.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xil_testmem.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xil_types.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xl2cc.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xl2cc_counter.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xparameters.h (81%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xparameters_ps.h (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xplatform_info.h (88%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xpm_counter.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xpseudo_asm.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src => system_bsp/ps7_cortexa9_0/include}/xpseudo_asm_gcc.h (96%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xqspips.h (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xqspips_hw.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xreg_cortexa9.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xscugic.h (92%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xscugic_hw.h (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xscutimer.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xscutimer_hw.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xscuwdt.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xscuwdt_hw.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src => system_bsp/ps7_cortexa9_0/include}/xsdps.h (94%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src => system_bsp/ps7_cortexa9_0/include}/xsdps_hw.h (96%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xstatus.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src => system_bsp/ps7_cortexa9_0/include}/xtime_l.h (90%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xuartps.h (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src => system_bsp/ps7_cortexa9_0/include}/xuartps_hw.h (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src => system_bsp/ps7_cortexa9_0/include}/xusbps.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src => system_bsp/ps7_cortexa9_0/include}/xusbps_endpoint.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/include/xusbps_hw.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src}/xcoresightpsdcc.h (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_4 => system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6}/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src}/xcpu_cortexa9.h (86%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src}/xddrps.h (96%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5}/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5}/src/xdevcfg.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src}/xdevcfg.h (97%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5}/src/xdevcfg_g.c (96%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5}/src/xdevcfg_hw.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5}/src/xdevcfg_hw.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5}/src/xdevcfg_intr.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5}/src/xdevcfg_selftest.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5}/src/xdevcfg_sinit.c (93%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c (96%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7}/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7}/src/xemacps.c (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src}/xemacps.h (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src}/xemacps_bd.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7}/src/xemacps_bdring.c (97%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src}/xemacps_bdring.h (97%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7}/src/xemacps_control.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7}/src/xemacps_g.c (93%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7}/src/xemacps_hw.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7}/src/xemacps_hw.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7}/src/xemacps_intr.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7}/src/xemacps_sinit.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/gpio_v4_3/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src}/xgpio.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_extra.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_g.c (86%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_i.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_intr.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src}/xgpio_l.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_selftest.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_sinit.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2 => system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3}/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2 => system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3}/src/xgpiops.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src}/xgpiops.h (95%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2 => system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3}/src/xgpiops_g.c (96%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2 => system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3}/src/xgpiops_hw.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2 => system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3}/src/xgpiops_hw.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2 => system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3}/src/xgpiops_intr.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2 => system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3}/src/xgpiops_selftest.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2 => system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3}/src/xgpiops_sinit.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5 => system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7}/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5 => system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7}/src/xiicps.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5 => system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7}/src/xiicps.h (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5 => system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7}/src/xiicps_g.c (97%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5 => system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7}/src/xiicps_hw.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src}/xiicps_hw.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5 => system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7}/src/xiicps_intr.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5 => system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7}/src/xiicps_master.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5 => system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7}/src/xiicps_options.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5 => system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7}/src/xiicps_selftest.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5 => system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7}/src/xiicps_sinit.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5 => system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7}/src/xiicps_slave.c (99%)
rename quad/xsdk_workspace_vivado/{quad_wrapper_hw_platform_0/drivers => system_bsp/ps7_cortexa9_0/libsrc}/pwm_recorder_v1_0/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{quad_wrapper_hw_platform_0/drivers => system_bsp/ps7_cortexa9_0/libsrc}/pwm_recorder_v1_0/src/pwm_recorder.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src}/pwm_recorder.h (100%)
rename quad/xsdk_workspace_vivado/{quad_wrapper_hw_platform_0/drivers => system_bsp/ps7_cortexa9_0/libsrc}/pwm_recorder_v1_0/src/pwm_recorder_selftest.c (100%)
rename quad/xsdk_workspace_vivado/{quad_wrapper_hw_platform_0/drivers => system_bsp/ps7_cortexa9_0/libsrc}/pwm_signal_out_v1_0/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{quad_wrapper_hw_platform_0/drivers => system_bsp/ps7_cortexa9_0/libsrc}/pwm_signal_out_v1_0/src/pwm_signal_out.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src}/pwm_signal_out.h (100%)
rename quad/xsdk_workspace_vivado/{quad_wrapper_hw_platform_0/drivers => system_bsp/ps7_cortexa9_0/libsrc}/pwm_signal_out_v1_0/src/pwm_signal_out_selftest.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3 => system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4}/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3 => system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4}/src/xqspips.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3 => system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4}/src/xqspips.h (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3 => system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4}/src/xqspips_g.c (96%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3 => system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4}/src/xqspips_hw.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3 => system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4}/src/xqspips_hw.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3 => system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4}/src/xqspips_options.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3 => system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4}/src/xqspips_selftest.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3 => system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4}/src/xqspips_sinit.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6 => system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9}/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6 => system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9}/src/xscugic.c (93%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6 => system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9}/src/xscugic.h (92%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6 => system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9}/src/xscugic_g.c (92%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6 => system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9}/src/xscugic_hw.c (89%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6 => system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9}/src/xscugic_hw.h (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6 => system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9}/src/xscugic_intr.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6 => system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9}/src/xscugic_selftest.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6 => system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9}/src/xscugic_sinit.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c (96%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c (96%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2 => system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5}/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2 => system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5}/src/xsdps.c (88%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src}/xsdps.h (94%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2 => system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5}/src/xsdps_g.c (94%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src}/xsdps_hw.h (96%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2 => system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5}/src/xsdps_options.c (94%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2 => system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5}/src/xsdps_sinit.c (97%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/_exit.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/_open.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/_sbrk.c (95%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/abort.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/asm_vectors.S (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/boot.S (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/bspconfig.h (89%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/changelog.txt (82%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/close.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/config.make (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/cpu_init.S (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/errno.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/fcntl.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/fstat.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/getpid.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/inbyte.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/isatty.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/kill.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/lseek.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/open.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/outbyte.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/print.c (90%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/profile/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/profile/_profile_clean.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/profile/_profile_init.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/profile/_profile_timer_hw.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/profile/_profile_timer_hw.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/profile/dummy.S (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/profile/mblaze_nt_types.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/profile/profile.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/profile/profile_cg.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/profile/profile_config.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/profile/profile_hist.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/profile/profile_mcount_arm.S (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/profile/profile_mcount_mb.S (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/profile/profile_mcount_ppc.S (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/putnum.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/read.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/sbrk.c (94%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/sleep.c (80%)
create mode 100644 quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.h
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/smc.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/translation_table.S (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/unlink.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/usleep.c (83%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/vectors.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/vectors.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/write.c (93%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xbasic_types.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xdebug.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xenv.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xenv_standalone.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil-crt0.S (91%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_assert.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_assert.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_cache.c (97%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_cache.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_cache_l.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_cache_vxworks.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src}/xil_errata.h (96%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_exception.c (86%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src}/xil_exception.h (97%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_hal.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_io.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src}/xil_io.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_macroback.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_mem.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_mem.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_misc_psreset_api.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_misc_psreset_api.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_mmu.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_mmu.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_printf.c (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src}/xil_printf.h (91%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_sinit.c => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleepcommon.c} (56%)
create mode 100644 quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.c
create mode 100644 quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.h
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_testcache.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_testcache.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_testio.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_testio.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_testmem.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_testmem.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xil_types.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xl2cc.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xl2cc_counter.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xl2cc_counter.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xparameters_ps.h (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xplatform_info.c (77%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xplatform_info.h (88%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xpm_counter.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xpm_counter.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xpseudo_asm.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src}/xpseudo_asm_gcc.h (96%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xreg_cortexa9.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xstatus.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2 => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7}/src/xtime_l.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src}/xtime_l.h (90%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6}/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6}/src/xuartps.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6}/src/xuartps.h (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6}/src/xuartps_g.c (97%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6}/src/xuartps_hw.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src}/xuartps_hw.h (98%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6}/src/xuartps_intr.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6}/src/xuartps_options.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6}/src/xuartps_selftest.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4 => system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6}/src/xuartps_sinit.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/usbps_v2_4/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src}/xusbps.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src}/xusbps_endpoint.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c (96%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/Makefile (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0/ps7_cortexa9_0/include => system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src}/xadcps.h (99%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c (96%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_intr.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c (100%)
rename quad/xsdk_workspace_vivado/{standalone_bsp_0 => system_bsp}/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c (100%)
diff --git a/quad/.gitignore b/quad/.gitignore
index adada7469..0b27dfb49 100644
--- a/quad/.gitignore
+++ b/quad/.gitignore
@@ -15,4 +15,5 @@ xsdk_workspace_vivado/design_1_wrapper_hw_platform_0/
**/xelab.pb
**/xelab.log
**/vivado_pid*.str
-**/*.tmp
\ No newline at end of file
+**/*.tmp
+**/*.o
\ No newline at end of file
diff --git a/quad/src/quad_app/initialize_components.c b/quad/src/quad_app/initialize_components.c
index edccbbbf8..4805f1d64 100644
--- a/quad/src/quad_app/initialize_components.c
+++ b/quad/src/quad_app/initialize_components.c
@@ -54,14 +54,6 @@ int init_structs(modular_structs_t *structs) {
// Initialize loop timers
struct TimerDriver *global_timer = &structs->hardware_struct.global_timer;
- struct TimerDriver *axi_timer = &structs->hardware_struct.axi_timer;
- if (global_timer->reset(global_timer)) {
- return -1;
- }
- if (axi_timer->reset(axi_timer)) {
- return -1;
- }
- timer_init_globals(global_timer, axi_timer);
// Initialize UART0
struct UARTDriver *uart = &structs->hardware_struct.uart_0;
diff --git a/quad/src/quad_app/type_def.h b/quad/src/quad_app/type_def.h
index 4d61cb1f0..52b99b536 100644
--- a/quad/src/quad_app/type_def.h
+++ b/quad/src/quad_app/type_def.h
@@ -493,7 +493,6 @@ typedef struct hardware_t {
struct GPSDriver gps;
struct CommDriver comm;
struct TimerDriver global_timer;
- struct TimerDriver axi_timer;
struct LEDDriver mio7_led;
struct SystemDriver sys;
struct IMUDriver imu;
diff --git a/quad/xsdk_workspace_vivado/.gitignore b/quad/xsdk_workspace_vivado/.gitignore
deleted file mode 100644
index ca597b529..000000000
--- a/quad/xsdk_workspace_vivado/.gitignore
+++ /dev/null
@@ -1,11 +0,0 @@
-SDK.log
-test.log
-.metadata/
-system_bsp/ps7_cortexa9_0/
-system_bsp/libgen.log
-zybo_fsbl_bsp/ps7_cortexa9_0/
-zybo_fsbl_bsp/libgen.log
-zybo_fsbl/Release
-zybo_fsbl/Debug
-zybo_fsbl/bootimage
-TAGS
diff --git a/quad/xsdk_workspace_vivado/README.md b/quad/xsdk_workspace_vivado/README.md
deleted file mode 100644
index bddc1b7c5..000000000
--- a/quad/xsdk_workspace_vivado/README.md
+++ /dev/null
@@ -1,30 +0,0 @@
-# XSDK Workspace
-
-This directory is reserved for Xilinx XSDK projects and their respective hardware platforms.
-
-## What is XSDK
-
-XSDK is a development tool made by Xilinx to create the files necessary to boot
- the hardware and software on the FPGA. It includes a test editor based on
- eclipse so the tools should feel vaguely familiar.
- Use our [how to use XSDK document](../doc/how_to_use_XSDK.md) or
- [XSDK documentation webpage](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/SDK_Doc/index.html)
-
-
-## Setup
-XSDK, being based on Eclipse, is rather fragile, so do yourself a favor
-and read this section so things get setup correctly.
-
-1. When you first open eclipse, select this directory, `xsdk_workspace`, as
- your workspace (see what we did there?).
-
-2. When you get to your workbench, your project pane should be empty. To
- add these projects, right-click on the project pane, and click on something
- like "import projects".
-
- 1. Select "Import Existing Projects" (wherever that is)
- 2. And then select the xsdk_workspace as the folder where you want to import
- projects. Add them all.
-
-3. If things are going swimmingly, then you should be able to build everything
- and be off on your merry embedded endeavors.
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper.hdf b/quad/xsdk_workspace_vivado/quad_wrapper.hdf
deleted file mode 100644
index 1cc1dd50b83f139908f6267bd401a6d9bbc35cf6..0000000000000000000000000000000000000000
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diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/.project b/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/.project
deleted file mode 100644
index 4b136bb87..000000000
--- a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/.project
+++ /dev/null
@@ -1,41 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
- <name>quad_wrapper_hw_platform_0</name>
- <comment>Created by SDK v2017.1</comment>
- <projects>
- </projects>
- <buildSpec>
- </buildSpec>
- <natures>
- <nature>com.xilinx.sdk.hw.HwProject</nature>
- </natures>
- <filteredResources>
- <filter>
- <id>1512948894437</id>
- <name></name>
- <type>6</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.xml</arguments>
- </matcher>
- </filter>
- <filter>
- <id>1512948894441</id>
- <name></name>
- <type>6</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.svd</arguments>
- </matcher>
- </filter>
- <filter>
- <id>1512948894444</id>
- <name></name>
- <type>6</type>
- <matcher>
- <id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.hwh</arguments>
- </matcher>
- </filter>
- </filteredResources>
-</projectDescription>
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/data/pwm_recorder.mdd b/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/data/pwm_recorder.mdd
deleted file mode 100644
index 2e60f72be..000000000
--- a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/data/pwm_recorder.mdd
+++ /dev/null
@@ -1,10 +0,0 @@
-
-
-OPTION psf_version = 2.1;
-
-BEGIN DRIVER pwm_recorder
- OPTION supported_peripherals = (pwm_recorder);
- OPTION copyfiles = all;
- OPTION VERSION = 1.0;
- OPTION NAME = pwm_recorder;
-END DRIVER
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/data/pwm_recorder.tcl b/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/data/pwm_recorder.tcl
deleted file mode 100644
index 7b50311bc..000000000
--- a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/data/pwm_recorder.tcl
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-proc generate {drv_handle} {
- xdefine_include_file $drv_handle "xparameters.h" "pwm_recorder" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR"
-}
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/data/pwm_signal_out.mdd b/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/data/pwm_signal_out.mdd
deleted file mode 100644
index c3b8f3c47..000000000
--- a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/data/pwm_signal_out.mdd
+++ /dev/null
@@ -1,10 +0,0 @@
-
-
-OPTION psf_version = 2.1;
-
-BEGIN DRIVER pwm_signal_out
- OPTION supported_peripherals = (pwm_signal_out);
- OPTION copyfiles = all;
- OPTION VERSION = 1.0;
- OPTION NAME = pwm_signal_out;
-END DRIVER
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/data/pwm_signal_out.tcl b/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/data/pwm_signal_out.tcl
deleted file mode 100644
index 14022c201..000000000
--- a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/data/pwm_signal_out.tcl
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-proc generate {drv_handle} {
- xdefine_include_file $drv_handle "xparameters.h" "pwm_signal_out" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR"
-}
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init.c b/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init.c
deleted file mode 100644
index 94bc6c494..000000000
--- a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init.c
+++ /dev/null
@@ -1,13125 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy of this
-* software and associated documentation files (the "Software"), to deal in the Software
-* without restriction, including without limitation the rights to use, copy, modify, merge,
-* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
-* persons to whom the Software is furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in all copies or
-* substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
-* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or
-* otherwise to promote the sale, use or other dealings in this Software without prior written
-* authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.c
-*
-* This file is automatically generated
-*
-*****************************************************************************/
-
-#include "ps7_init.h"
-
-unsigned long ps7_pll_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x177
- // .. .. ==> 0XF8000110[21:12] = 0x00000177U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1a
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1db
- // .. .. ==> 0XF8000114[21:12] = 0x000001DBU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x15
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000118[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x34
- // .. ==> 0XF8000128[13:8] = 0x00000034U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003400U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000154[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xa
- // .. ==> 0XF8000154[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
- // .. .. START: TRACE CLOCK
- // .. .. FINISH: TRACE CLOCK
- // .. .. CLKACT = 0x1
- // .. .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR = 0x5
- // .. .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // .. ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR0 = 0x5
- // .. .. ==> 0XF8000170[13:8] = 0x00000005U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // .. .. DIVISOR1 = 0x2
- // .. .. ==> 0XF8000170[25:20] = 0x00000002U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
- // .. .. CLK_621_TRUE = 0x1
- // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. .. DMA_CPU_2XCLKACT = 0x1
- // .. .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. USB0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. USB1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. .. GEM0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. .. GEM1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. SDI0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. .. SDI1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. SPI0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. SPI1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. CAN0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. CAN1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. I2C0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. .. I2C1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. .. UART0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. .. UART1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. GPIO_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. .. LQSPI_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. .. SMC_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_3_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f
- // .. .. ==> 0XF8006004[11:0] = 0x0000007FU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU
- // .. .. reserved_reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x0000107FU),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1a
- // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
- // .. .. reg_ddrc_t_rfc_min = 0x54
- // .. .. ==> 0XF8006014[13:6] = 0x00000054U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x15
- // .. .. ==> 0XF8006018[15:10] = 0x00000015U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U
- // .. .. reg_ddrc_t_ras_max = 0x23
- // .. .. ==> 0XF8006018[21:16] = 0x00000023U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U
- // .. .. reg_ddrc_t_ras_min = 0x13
- // .. .. ==> 0XF8006018[26:22] = 0x00000013U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x6
- // .. .. ==> 0XF8006020[7:5] = 0x00000006U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x167
- // .. .. ==> 0XF8006034[13:4] = 0x00000167U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011674U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x6
- // .. .. ==> 0XF8006078[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_t_cksrx = 0x6
- // .. .. ==> 0XF8006078[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xc845
- // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U
- // .. .. dram_rstn_x1024 = 0x67
- // .. .. ==> 0XF80060A8[27:20] = 0x00000067U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8f
- // .. .. ==> 0XF800612C[19:10] = 0x0000008FU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8a
- // .. .. ==> 0XF8006130[19:10] = 0x0000008AU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8b
- // .. .. ==> 0XF8006134[19:10] = 0x0000008BU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x92
- // .. .. ==> 0XF8006138[19:10] = 0x00000092U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. .. ==> 0XF8006154[9:0] = 0x00000077U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. .. ==> 0XF8006158[9:0] = 0x0000007CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. .. ==> 0XF800615C[9:0] = 0x0000007CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x75
- // .. .. ==> 0XF8006160[9:0] = 0x00000075U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe4
- // .. .. ==> 0XF8006168[10:0] = 0x000000E4U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xdf
- // .. .. ==> 0XF800616C[10:0] = 0x000000DFU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe0
- // .. .. ==> 0XF8006170[10:0] = 0x000000E0U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe7
- // .. .. ==> 0XF8006174[10:0] = 0x000000E7U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. .. ==> 0XF8006180[9:0] = 0x000000BCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. .. ==> 0XF8006184[9:0] = 0x000000BCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb5
- // .. .. ==> 0XF8006188[9:0] = 0x000000B5U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U),
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa6
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A6U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B00[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. reserved_SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x0
- // .. ==> 0XF8000B6C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B6C[4:1] = 0x00000000U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
- // .. VREF_EXT_EN = 0x3
- // .. ==> 0XF8000B6C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. reserved_VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. reserved_REFIO_TEST = 0x0
- // .. ==> 0XF8000B6C[11:10] = 0x00000000U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
- // .. reserved_REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reserved_VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reserved_VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reserved_VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reserved_VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reserved_VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reserved_INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reserved_TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reserved_TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reserved_TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. reserved_TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reserved_INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000704[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000708[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800070C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000710[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000714[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000718[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000720[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000728[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF800072C[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000730[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000734[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800073C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000740[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000744[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000748[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800074C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000750[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000754[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000758[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800075C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000760[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000764[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000768[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800076C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000770[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000774[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000778[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800077C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000780[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000784[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000788[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800078C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000790[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000794[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000798[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800079C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A8[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007AC[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007B8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007BC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007C8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007CC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007D0[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007D4[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000200U),
- // .. SDIO0_WP_SEL = 55
- // .. ==> 0XF8000830[5:0] = 0x00000037U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000037U
- // .. SDIO0_CD_SEL = 47
- // .. ==> 0XF8000830[21:16] = 0x0000002FU
- // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0001018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
- // .. BDIV = 0x6
- // .. ==> 0XE0000034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0000018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0000000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0000000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0000000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0000000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0000000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0000000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0000000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0000000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0000000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
- // .. CHMODE = 0x0
- // .. ==> 0XE0000004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0000004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0000004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0000004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0000004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. DIRECTION_1 = 0x4000
- // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. OP_ENABLE_1 = 0x4000
- // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x0
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_LVL_INP_EN_0 = 1
- // .. ==> 0XF8000900[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. USER_LVL_OUT_EN_0 = 1
- // .. ==> 0XF8000900[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USER_LVL_INP_EN_1 = 1
- // .. ==> 0XF8000900[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. USER_LVL_OUT_EN_1 = 1
- // .. ==> 0XF8000900[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. reserved_FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. reserved_FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reserved_FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reserved_FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reserved_FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. reserved_FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. .. START: AFI2 SECURE REGISTER
- // .. .. FINISH: AFI2 SECURE REGISTER
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x177
- // .. .. ==> 0XF8000110[21:12] = 0x00000177U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1a
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1db
- // .. .. ==> 0XF8000114[21:12] = 0x000001DBU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x15
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000118[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x34
- // .. ==> 0XF8000128[13:8] = 0x00000034U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003400U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000154[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xa
- // .. ==> 0XF8000154[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
- // .. .. START: TRACE CLOCK
- // .. .. FINISH: TRACE CLOCK
- // .. .. CLKACT = 0x1
- // .. .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR = 0x5
- // .. .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // .. ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR0 = 0x5
- // .. .. ==> 0XF8000170[13:8] = 0x00000005U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // .. .. DIVISOR1 = 0x2
- // .. .. ==> 0XF8000170[25:20] = 0x00000002U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
- // .. .. CLK_621_TRUE = 0x1
- // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. .. DMA_CPU_2XCLKACT = 0x1
- // .. .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. USB0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. USB1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. .. GEM0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. .. GEM1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. SDI0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. .. SDI1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. SPI0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. SPI1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. CAN0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. CAN1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. I2C0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. .. I2C1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. .. UART0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. .. UART1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. GPIO_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. .. LQSPI_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. .. SMC_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_2_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f
- // .. .. ==> 0XF8006004[11:0] = 0x0000007FU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x0008107FU),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1a
- // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
- // .. .. reg_ddrc_t_rfc_min = 0x54
- // .. .. ==> 0XF8006014[13:6] = 0x00000054U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x15
- // .. .. ==> 0XF8006018[15:10] = 0x00000015U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U
- // .. .. reg_ddrc_t_ras_max = 0x23
- // .. .. ==> 0XF8006018[21:16] = 0x00000023U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U
- // .. .. reg_ddrc_t_ras_min = 0x13
- // .. .. ==> 0XF8006018[26:22] = 0x00000013U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x6
- // .. .. ==> 0XF8006020[7:5] = 0x00000006U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x167
- // .. .. ==> 0XF8006034[13:4] = 0x00000167U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011674U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x6
- // .. .. ==> 0XF8006078[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_t_cksrx = 0x6
- // .. .. ==> 0XF8006078[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xc845
- // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U
- // .. .. dram_rstn_x1024 = 0x67
- // .. .. ==> 0XF80060A8[27:20] = 0x00000067U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8f
- // .. .. ==> 0XF800612C[19:10] = 0x0000008FU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8a
- // .. .. ==> 0XF8006130[19:10] = 0x0000008AU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8b
- // .. .. ==> 0XF8006134[19:10] = 0x0000008BU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x92
- // .. .. ==> 0XF8006138[19:10] = 0x00000092U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. .. ==> 0XF8006154[9:0] = 0x00000077U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. .. ==> 0XF8006158[9:0] = 0x0000007CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. .. ==> 0XF800615C[9:0] = 0x0000007CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x75
- // .. .. ==> 0XF8006160[9:0] = 0x00000075U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe4
- // .. .. ==> 0XF8006168[10:0] = 0x000000E4U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xdf
- // .. .. ==> 0XF800616C[10:0] = 0x000000DFU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe0
- // .. .. ==> 0XF8006170[10:0] = 0x000000E0U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe7
- // .. .. ==> 0XF8006174[10:0] = 0x000000E7U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. .. ==> 0XF8006180[9:0] = 0x000000BCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. .. ==> 0XF8006184[9:0] = 0x000000BCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb5
- // .. .. ==> 0XF8006188[9:0] = 0x000000B5U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U),
- // .. .. reg_phy_loopback = 0x0
- // .. .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_use_rank0_delays = 0x1
- // .. .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_phy_int_lpbk = 0x0
- // .. .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_per_bank_refresh = 0x0
- // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa6
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A6U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. CLK_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. SRSTN_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x0
- // .. ==> 0XF8000B6C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B6C[4:1] = 0x00000000U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
- // .. VREF_EXT_EN = 0x3
- // .. ==> 0XF8000B6C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_TEST = 0x0
- // .. ==> 0XF8000B6C[11:10] = 0x00000000U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000704[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000708[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800070C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000710[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000714[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000718[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000720[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000728[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF800072C[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000730[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000734[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800073C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000740[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000744[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000748[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800074C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000750[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000754[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000758[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800075C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000760[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000764[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000768[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800076C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000770[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000774[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000778[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800077C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000780[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000784[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000788[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800078C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000790[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000794[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000798[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800079C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A8[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007AC[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007B8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007BC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007C8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007CC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007D0[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007D4[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000200U),
- // .. SDIO0_WP_SEL = 55
- // .. ==> 0XF8000830[5:0] = 0x00000037U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000037U
- // .. SDIO0_CD_SEL = 47
- // .. ==> 0XF8000830[21:16] = 0x0000002FU
- // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0001018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. BDIV = 0x6
- // .. ==> 0XE0000034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0000018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0000000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0000000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0000000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0000000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0000000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0000000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0000000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0000000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0000000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0000004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0000004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0000004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0000004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0000004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0000004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0000004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. DIRECTION_1 = 0x4000
- // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. OP_ENABLE_1 = 0x4000
- // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x0
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x177
- // .. .. ==> 0XF8000110[21:12] = 0x00000177U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1a
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1db
- // .. .. ==> 0XF8000114[21:12] = 0x000001DBU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x15
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000118[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x34
- // .. ==> 0XF8000128[13:8] = 0x00000034U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003400U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000154[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xa
- // .. ==> 0XF8000154[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
- // .. .. START: TRACE CLOCK
- // .. .. FINISH: TRACE CLOCK
- // .. .. CLKACT = 0x1
- // .. .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR = 0x5
- // .. .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // .. ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR0 = 0x5
- // .. .. ==> 0XF8000170[13:8] = 0x00000005U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // .. .. DIVISOR1 = 0x2
- // .. .. ==> 0XF8000170[25:20] = 0x00000002U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
- // .. .. CLK_621_TRUE = 0x1
- // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. .. DMA_CPU_2XCLKACT = 0x1
- // .. .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. USB0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. USB1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. .. GEM0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. .. GEM1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. SDI0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. .. SDI1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. SPI0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. SPI1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. CAN0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. CAN1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. I2C0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. .. I2C1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. .. UART0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. .. UART1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. GPIO_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. .. LQSPI_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. .. SMC_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_1_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f
- // .. .. ==> 0XF8006004[11:0] = 0x0000007FU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x0008107FU),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1a
- // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
- // .. .. reg_ddrc_t_rfc_min = 0x54
- // .. .. ==> 0XF8006014[13:6] = 0x00000054U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x15
- // .. .. ==> 0XF8006018[15:10] = 0x00000015U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U
- // .. .. reg_ddrc_t_ras_max = 0x23
- // .. .. ==> 0XF8006018[21:16] = 0x00000023U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U
- // .. .. reg_ddrc_t_ras_min = 0x13
- // .. .. ==> 0XF8006018[26:22] = 0x00000013U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x6
- // .. .. ==> 0XF8006020[7:5] = 0x00000006U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x167
- // .. .. ==> 0XF8006034[13:4] = 0x00000167U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011674U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xc845
- // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U
- // .. .. dram_rstn_x1024 = 0x67
- // .. .. ==> 0XF80060A8[27:20] = 0x00000067U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8f
- // .. .. ==> 0XF800612C[19:10] = 0x0000008FU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8a
- // .. .. ==> 0XF8006130[19:10] = 0x0000008AU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8b
- // .. .. ==> 0XF8006134[19:10] = 0x0000008BU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x92
- // .. .. ==> 0XF8006138[19:10] = 0x00000092U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. .. ==> 0XF8006154[9:0] = 0x00000077U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. .. ==> 0XF8006158[9:0] = 0x0000007CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. .. ==> 0XF800615C[9:0] = 0x0000007CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x75
- // .. .. ==> 0XF8006160[9:0] = 0x00000075U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe4
- // .. .. ==> 0XF8006168[10:0] = 0x000000E4U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xdf
- // .. .. ==> 0XF800616C[10:0] = 0x000000DFU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe0
- // .. .. ==> 0XF8006170[10:0] = 0x000000E0U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe7
- // .. .. ==> 0XF8006174[10:0] = 0x000000E7U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. .. ==> 0XF8006180[9:0] = 0x000000BCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. .. ==> 0XF8006184[9:0] = 0x000000BCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb5
- // .. .. ==> 0XF8006188[9:0] = 0x000000B5U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U),
- // .. .. reg_phy_loopback = 0x0
- // .. .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_use_rank0_delays = 0x1
- // .. .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_phy_int_lpbk = 0x0
- // .. .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_per_bank_refresh = 0x0
- // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa6
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A6U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. CLK_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. SRSTN_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x0
- // .. ==> 0XF8000B6C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B6C[4:1] = 0x00000000U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
- // .. VREF_EXT_EN = 0x3
- // .. ==> 0XF8000B6C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000704[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000708[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800070C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000710[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000714[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000718[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000720[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000728[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF800072C[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000730[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000734[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800073C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000740[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000744[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000748[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800074C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000750[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000754[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000758[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800075C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000760[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000764[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000768[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800076C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000770[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000774[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000778[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800077C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000780[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000784[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000788[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800078C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000790[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000794[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000798[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800079C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A8[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007AC[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007B8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007BC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007C8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007CC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007D0[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007D4[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000200U),
- // .. SDIO0_WP_SEL = 55
- // .. ==> 0XF8000830[5:0] = 0x00000037U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000037U
- // .. SDIO0_CD_SEL = 47
- // .. ==> 0XF8000830[21:16] = 0x0000002FU
- // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0001018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. BDIV = 0x6
- // .. ==> 0XE0000034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0000018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0000000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0000000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0000000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0000000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0000000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0000000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0000000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0000000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0000000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0000004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0000004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0000004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0000004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0000004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0000004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0000004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. DIRECTION_1 = 0x4000
- // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. OP_ENABLE_1 = 0x4000
- // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x0
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-
-#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
-
-unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
-unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
-unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
-unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-
-int
-ps7_post_config()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_post_config_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_post_config_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_post_config_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-
-int
-ps7_init()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret;
- //int pcw_ver = 0;
-
- if (si_ver == PCW_SILICON_VERSION_1) {
- ps7_mio_init_data = ps7_mio_init_data_1_0;
- ps7_pll_init_data = ps7_pll_init_data_1_0;
- ps7_clock_init_data = ps7_clock_init_data_1_0;
- ps7_ddr_init_data = ps7_ddr_init_data_1_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
- //pcw_ver = 1;
-
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ps7_mio_init_data = ps7_mio_init_data_2_0;
- ps7_pll_init_data = ps7_pll_init_data_2_0;
- ps7_clock_init_data = ps7_clock_init_data_2_0;
- ps7_ddr_init_data = ps7_ddr_init_data_2_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
- //pcw_ver = 2;
-
- } else {
- ps7_mio_init_data = ps7_mio_init_data_3_0;
- ps7_pll_init_data = ps7_pll_init_data_3_0;
- ps7_clock_init_data = ps7_clock_init_data_3_0;
- ps7_ddr_init_data = ps7_ddr_init_data_3_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
- //pcw_ver = 3;
- }
-
- // MIO init
- ret = ps7_config (ps7_mio_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // PLL init
- ret = ps7_config (ps7_pll_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // Clock init
- ret = ps7_config (ps7_clock_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // DDR init
- ret = ps7_config (ps7_ddr_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
-
-
- // Peripherals init
- ret = ps7_config (ps7_peripherals_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
- //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
- return PS7_INIT_SUCCESS;
-}
-
-
-
-
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
-
-
-
-
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init.h b/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init.h
deleted file mode 100644
index b88f82a5f..000000000
--- a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init.h
+++ /dev/null
@@ -1,137 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy of this
-* software and associated documentation files (the "Software"), to deal in the Software
-* without restriction, including without limitation the rights to use, copy, modify, merge,
-* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
-* persons to whom the Software is furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in all copies or
-* substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
-* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or
-* otherwise to promote the sale, use or other dealings in this Software without prior written
-* authorization from Xilinx.
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 650000000
-#define DDR_FREQ 525000000
-#define DCI_FREQ 10096154
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 100000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 108333336
-#define WDT_FREQ 108333336
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 10000000
-#define FPGA2_FREQ 10000000
-#define FPGA3_FREQ 10000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init.html b/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init.html
deleted file mode 100644
index b794a3427..000000000
--- a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init.html
+++ /dev/null
@@ -1,142728 +0,0 @@
-<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.0//EN" "http://www.w3.org/TR/REC-html40/strict.dtd">
-<html lang="en">
-<head>
-<meta http-equiv="content-type" content="text/html;charset=UTF-8">
-<title>Zynq PS configuration detail</title>
-<style type="text/css">.sitename { background-color: #EEE;border:2px ridge #FFCF01;color: #B20838; font-size:22px; font-style:oblique; font-weight:bold;margin:0px 0px 10px 0px;padding:5px 0px; text-align:center; z-index: 3; -moz-border-radius: 10px; -webkit-border-radius: 10px; -khtml-border-radius: 10px; border-radius: 10px;}.navpath {color: #FFCF01; font-size:8px;padding: 7px 2px 2px 11px; text-transform: capitalize; z-index:2;}.navbar { background-color: #B20838; background-color: #EE3424;color: #fff;border: 1px solid #000; border-left: 0px solid #000; border-right: 0px solid #000; font-family: arial, sans-serif; font-weight: bold;height:50px; letter-spacing: 2px; text-transform: uppercase;position:fixed;top:0px;left:0px;right:0px; z-index: 0; /* -moz-border-radius: 10px; -webkit-border-radius: 10px; -khtml-border-radius: 10px; border-radius: 10px; */}.navlink_container { text-align:center;position: absolute;bottom:-1px;}.navbar a {color: #FFF;}.navbar a:hover {color: #EC891D;}.navbar ul { margin-left: 0px;height: 70px;overflow: hidden;}.navbar li { background-color: #B20838;padding: 4px 400px 4px 400px;float: left; font-size:24px;width: 800px;}.navbar li:hover { background-color: #000;color: #eee;}.navbar li#last { padding-right: 10px; border-right: 1px solid #050505; background-image: none;}.nav_splash {width: 80%;float:right; z-index: 0;}.search_form {position:fixed;top:25px;right:5px; z-index:2;}.action_tray {padding:5px;position: fixed;top: 57px;width: 210px;}.action_tray_header { text-align: center; background-color: #DDD;border: 2px groove #FFCF01; margin-bottom: 10px; -moz-border-radius: 10px; -webkit-border-radius: 10px; -khtml-border-radius: 10px; border-radius: 10px;}.action_tray_header:hover { background-color: #eee;}.action_container {padding:10px 5px; text-align: center;}.action { background-color: #FFF;border: 1px outset #B20838;padding: 5px 0px; font-weight:bolder; margin-bottom: 2px; -moz-border-radius: 7px; -webkit-border-radius: 7px; -khtml-border-radius: 7px; border-radius: 7px; text-transform:uppercase;color: #B20838; }.action:hover {border: 1px inset #000; background-color: #FFCF01;color: #000;}.content_container { background-color:#fff;border: 0px solid #000; border-left: 1px solid #000;color: #000;overflow:auto;padding: 10px;position:fixed;left: 224px;top: 52px;right: 0px;bottom:0px; text-align: left; padding-right:25px; z-index:1;}.SelectButtons { background-color:white; border-width:1px 1px 1px 1px; border-style:solid; border-color:black;margin:10px 10px 10px 0px; z-index:2; -moz-border-radius: 5px; -webkit-border-radius: 5px; -khtml-border-radius: 5px; border-radius: 5px; font-weight:bold;}address { margin-top: 1em; padding-top: 1em; border-top: thin dotted }.viewButtons { background-color:#F3F781; border-width:1px 1px 1px 1px; border-style:solid; border-color:black;margin:10px 0px 10px 0px; z-index:2; -moz-border-radius: 5px; -webkit-border-radius: 5px; -khtml-border-radius: 5px; border-radius: 5px; font-weight:bold;}address { margin-top: 1em; padding-top: 1em; border-top: thin dotted }.db_selector {margin:10px 0px 10px 0px;}.db_selector_title { background-color: #00FFFF;border: 1px solid #000; margin-bottom:5px; font-weight:bold;padding:5px 3px; -moz-border-radius: 5px; -webkit-border-radius: 5px; -khtml-border-radius: 5px; border-radius: 5px;}select { background-color: #FFEFC0; font-weight:bolder;padding:3px; -moz-border-radius: 5px; -webkit-border-radius: 5px; -khtml-border-radius: 5px; border-radius: 5px;}select:hover { background-color: #AFEFF0; }</style>
-<script type="text/javascript" language="JavaScript">function ChangeSilRegLink(id) { var ver=document.getElementById(id).value; if (ver == "Silicon3.0") { document.getElementById("MIO_Registers").href="#ps7_mio_init_data_3_0"; document.getElementById("PLL_Registers").href="#ps7_pll_init_data_3_0"; document.getElementById("Clock_Registers").href="#ps7_clock_init_data_3_0"; document.getElementById("DDR_Registers").href="#ps7_ddr_init_data_3_0"; document.getElementById("Peri_Registers").href="#ps7_peripherals_init_data_3_0"; window.location = '#ps7_mio_init_data_3_0'; } else if (ver == "Silicon2.0") { document.getElementById("MIO_Registers").href="#ps7_mio_init_data_2_0"; document.getElementById("PLL_Registers").href="#ps7_pll_init_data_2_0"; document.getElementById("Clock_Registers").href="#ps7_clock_init_data_2_0"; document.getElementById("DDR_Registers").href="#ps7_ddr_init_data_2_0"; document.getElementById("Peri_Registers").href="#ps7_peripherals_init_data_2_0"; window.location = '#ps7_mio_init_data_2_0'; } else { document.getElementById("MIO_Registers").href="#ps7_mio_init_data_1_0"; document.getElementById("PLL_Registers").href="#ps7_pll_init_data_1_0"; document.getElementById("Clock_Registers").href="#ps7_clock_init_data_1_0"; document.getElementById("DDR_Registers").href="#ps7_ddr_init_data_1_0"; document.getElementById("Peri_Registers").href="#ps7_peripherals_init_data_1_0"; window.location = '#ps7_mio_init_data_1_0'; }}</script>
-<body>
-<DIV class="navbar">
-<DIV class="navlink_container">
-<A id="Summary" href="#">
-<li>
-<DIV class="navlink">Zynq PS Register Summary Viewer
-</DIV>
-</li>
-</A>
-</DIV>
-</DIV>
-<DIV class="action_tray">
-<A id="Report" href="#">
-<DIV class="sitename">Zynq PS7 Summary Report
-</DIV>
-</A>
-<DIV class="viewButtons">User Configurations
-</DIV>
-<DIV class="viewButtons">
-<A id="MIO_Configurations" href="#ZynqPerTab">
-<DIV class="viewButtonHalf">MIO Configurations
-</DIV>
-</A>
-<HR class="action_separator">
-<A id="CLK_Configurations" href="#ClockInfoTab">
-<DIV class="viewButtonHalf">CLK Configurations
-</DIV>
-</A>
-<HR class="action_separator">
-<A id="DDR_Configurations" href="#DDRInfoTab">
-<DIV class="viewButtonHalf">DDR Configurations
-</DIV>
-</A>
-<HR class="action_separator">
-<A id="SMC_Configurations" href="#SMCInfoTab">
-<DIV class="viewButtonHalf">SMC Configurations
-</DIV>
-</A>
-</DIV>
-<DIV class="db_selector">
-<DIV class="db_selector_title">Select Version:
-<select id="db_selection" class="db_selection" onChange="ChangeSilRegLink(this.id)" width="210" style="width: 210px">
-<option value="Silicon3.0">Silicon 3.0</option>
-<option value="Silicon2.0">Silicon 2.0</option>
-<option value="Silicon1.0">Silicon 1.0</option>
-</select>
-</DIV>
-</DIV>
-<DIV class="viewButtons">Zynq Register View
-</DIV>
-<DIV class="action_container">
-<A id="MIO_Registers" href="#ps7_mio_init_data_3_0">
-<DIV class="action">MIO Registers
-</DIV>
-</A>
-<A id="PLL_Registers" href="#ps7_pll_init_data_3_0">
-<DIV class="action">PLL Registers
-</DIV>
-</A>
-<A id="Clock_Registers" href="#ps7_clock_init_data_3_0">
-<DIV class="action">Clock Registers
-</DIV>
-</A>
-<A id="DDR_Registers" href="#ps7_ddr_init_data_3_0">
-<DIV class="action">DDR Registers
-</DIV>
-</A>
-<A id="Peri_Registers" href="#ps7_peripherals_init_data_3_0">
-<DIV class="action">Peripherals Registers
-</DIV>
-</A>
-</DIV>
-<DIV class="content_container">This design is targeted for xc7z010 board (part number: xc7z010clg400-1)
-
-<br>
-<H1>Zynq Design Summary</H1>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=20% BGCOLOR=#C0C0FF>
-<B>Device</B>
-</TD>
-<TD width=80% BGCOLOR=#E6E6E6>
-xc7z010
-</TD>
-</TR>
-<TR valign="top">
-<TD width=20% BGCOLOR=#C0C0FF>
-<B>SpeedGrade</B>
-</TD>
-<TD width=80% BGCOLOR=#E6E6E6>
--1
-</TD>
-</TR>
-<TR valign="top">
-<TD width=20% BGCOLOR=#C0C0FF>
-<B>Part</B>
-</TD>
-<TD width=80% BGCOLOR=#E6E6E6>
-xc7z010clg400-1
-</TD>
-</TR>
-<TR valign="top">
-<TD width=20% BGCOLOR=#C0C0FF>
-<B>Description</B>
-</TD>
-<TD width=80% BGCOLOR=#E6E6E6>
-Zynq PS Configuration Report with register details
-</TD>
-</TR>
-<TR valign="top">
-<TD width=20% BGCOLOR=#C0C0FF>
-<B>Vendor</B>
-</TD>
-<TD width=80% BGCOLOR=#E6E6E6>
-Xilinx
-</TD>
-</TR>
-</TABLE>
-<H2><a name="ZynqPerTab">MIO Table View</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=10% BGCOLOR=#C0C0FF>
-<B>MIO Pin</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0FF>
-<B>Peripheral</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0FF>
-<B>Signal</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0FF>
-<B>IO Type</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0FF>
-<B>Speed</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0FF>
-<B>Pullup</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0FF>
-<B>Direction</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-GPIO
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-gpio[0]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 3.3V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-slow
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-enabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Quad SPI Flash
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-qspi0_ss_b
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 3.3V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-out
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Quad SPI Flash
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-qspi0_io[0]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 3.3V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Quad SPI Flash
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-qspi0_io[1]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 3.3V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Quad SPI Flash
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-qspi0_io[2]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 3.3V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Quad SPI Flash
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-qspi0_io[3]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 3.3V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Quad SPI Flash
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-qspi0_sclk
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 3.3V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-out
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-GPIO
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-gpio[7]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 3.3V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-slow
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-out
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Quad SPI Flash
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-qspi_fbclk
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 3.3V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-out
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-GPIO
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-gpio[9]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 3.3V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-slow
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-enabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-I2C 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-scl
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 3.3V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-slow
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-enabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-I2C 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-sda
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 3.3V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-slow
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-enabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-I2C 1
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-scl
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 3.3V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-slow
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-enabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-I2C 1
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-sda
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 3.3V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-slow
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-enabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-GPIO
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-gpio[14]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 3.3V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-slow
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-enabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-GPIO
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-gpio[15]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 3.3V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-slow
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-enabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Enet 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-tx_clk
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-HSTL 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-out
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Enet 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-txd[0]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-HSTL 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-out
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Enet 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-txd[1]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-HSTL 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-out
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Enet 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-txd[2]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-HSTL 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-out
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Enet 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-txd[3]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-HSTL 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-out
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Enet 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-tx_ctl
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-HSTL 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-out
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Enet 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-rx_clk
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-HSTL 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-in
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 23</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Enet 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-rxd[0]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-HSTL 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-in
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Enet 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-rxd[1]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-HSTL 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-in
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 25</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Enet 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-rxd[2]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-HSTL 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-in
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 26</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Enet 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-rxd[3]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-HSTL 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-in
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Enet 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-rx_ctl
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-HSTL 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-in
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-USB 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-data[4]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 29</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-USB 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-dir
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-in
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-USB 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-stp
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-out
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 31</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-USB 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-nxt
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-in
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-USB 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-data[0]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 33</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-USB 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-data[1]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 34</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-USB 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-data[2]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 35</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-USB 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-data[3]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 36</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-USB 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-clk
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-in
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 37</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-USB 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-data[5]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 38</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-USB 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-data[6]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 39</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-USB 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-data[7]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-SD 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-clk
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 41</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-SD 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-cmd
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 42</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-SD 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-data[0]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 43</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-SD 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-data[1]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 44</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-SD 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-data[2]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 45</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-SD 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-data[3]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-fast
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 46</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-USB Reset
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-reset
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-slow
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-enabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-out
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 47</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-SD 0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-cd
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-slow
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-in
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 48</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-UART 1
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-tx
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-slow
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-out
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 49</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-UART 1
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-rx
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-slow
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-in
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 50</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-GPIO
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-gpio[50]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-slow
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 51</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-GPIO
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-gpio[51]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-slow
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 52</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-GPIO
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-gpio[52]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-slow
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>MIO 53</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-GPIO
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-gpio[53]
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-LVCMOS 1.8V
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-slow
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-inout
-</TD>
-</TR>
-</TABLE>
-<H2><a name="DDRInfoTab">DDR Memory information</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=10% BGCOLOR=#E0F8F7>
-<B>Parameter name</B>
-</TD>
-<TD width=10% BGCOLOR=#E0F8F7>
-<B>Value</B>
-</TD>
-<TD width=10% BGCOLOR=#E0F8F7>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>Enable DDR</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-1
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Enable DDR Controller of Zynq PS
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>Enable DDR</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-1
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Enable DDR Controller of Zynq PS
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>Memory Part</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-MT41K128M16 JT-125
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>DRAM bus width</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-32 Bit
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ECC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Disabled
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-ECC is supported only for data width of 16-bit
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>BURST Length (lppdr only)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-8
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>Internal Vref</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>Operating Frequency (MHz)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-525
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>HIGH temperature</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Normal (0-85)
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Select the operating temparature
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>DRAM IC bus width</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-16 Bits
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Provide the width of the DRAM chip
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>DRAM Device Capacity</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-2048 MBits
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>Speed Bin</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-DDR3_1066F
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Provide the Speed Bin
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>BANK Address Count</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-3
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ROW Address Count</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-14
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Provide the Row address for ACTIVE commands
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>COLUMN Address Count</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-10
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Provide the Row address for READ/WRITE commands
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>CAS Latency</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-7
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>CAS Write Latency</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-6
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Select the CAS Write Latency
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RAS to CAS Delay</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-7
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RECHARGE Time</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-7
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>tRC (ns )</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-48.75
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Provide the Row cycle time tRC (ns)
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>tRASmin ( ns )</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-35.0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>tFAW</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-40.0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-It restricts the number of activates that can be done within a certain window of time
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ADDITIVE Latency</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-0
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>Write levelling</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-1
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>Read gate</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-1
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>Read gate</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-1
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>DQS to Clock delay [0] (ns)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
--0.073
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-The daly difference of each DQS path delay subtracted from the clock path delay
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>DQS to Clock delay [1] (ns)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
--0.034
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-The daly difference of each DQS path delay subtracted from the clock path delay
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>DQS to Clock delay [2] (ns)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
--0.03
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-The daly difference of each DQS path delay subtracted from the clock path delay
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>DQS to Clock delay [3] (ns)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
--0.082
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-The daly difference of each DQS path delay subtracted from the clock path delay
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>Board delay [0] (ns)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-0.176
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>Board delay [1] (ns)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-0.159
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>Board delay [2] (ns)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-0.162
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>Board delay [3] (ns)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-0.187
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
-</TD>
-</TR>
-</TABLE>
-<H2><a name="ClockInfoTab">PS Clocks information</a></H2>
-<H2><a name="ClockInfoTab">PS Reference Clock : 50.000000</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=10% BGCOLOR=#E0F8F7>
-<B>Peripheral</B>
-</TD>
-<TD width=10% BGCOLOR=#E0F8F7>
-<B>PLL source</B>
-</TD>
-<TD width=10% BGCOLOR=#E0F8F7>
-<B>Frequency (MHz)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>CPU 6x Freq (MHz)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-ARM PLL
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-650.000000
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>QSPI Flash Freq (MHz)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-IO PLL
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-200.000000
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ENET0 Freq (MHz)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-IO PLL
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-125.000000
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>SDIO Freq (MHz)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-IO PLL
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-50.000000
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>UART Freq (MHz)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-IO PLL
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-100.000000
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>UART Freq (MHz)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-IO PLL
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-100.000000
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>TTC0 CLK0 Freq (MHz)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-CPU_1X
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-108.333336
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>TTC0 CLK1 Freq (MHz)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-CPU_1X
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-108.333336
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>TTC0 CLK2 Freq (MHz)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-CPU_1X
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-108.333336
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>FPGA0 Freq (MHz)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-IO PLL
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-100.000000
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>FPGA1 Freq (MHz)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-IO PLL
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-10.000000
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>FPGA2 Freq (MHz)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-IO PLL
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-10.000000
-</TD>
-</TR>
-<TR valign="top">
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>FPGA3 Freq (MHz)</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-IO PLL
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-10.000000
-</TD>
-</TR>
-</TABLE>
-<H2><a name="ps7_pll_init_data_3_0">ps7_pll_init_data_3_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_UNLOCK">
-SLCR_UNLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CFG">
-ARM_PLL_CFG
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000110</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Configuration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CTRL">
-ARM_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CTRL">
-ARM_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CTRL">
-ARM_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CTRL">
-ARM_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CTRL">
-ARM_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_CLK_CTRL">
-ARM_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000120</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CPU Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CFG">
-DDR_PLL_CFG
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000114</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Configuration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CTRL">
-DDR_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CTRL">
-DDR_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CTRL">
-DDR_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CTRL">
-DDR_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CTRL">
-DDR_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_CLK_CTRL">
-DDR_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000124</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CFG">
-IO_PLL_CFG
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000118</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Configuration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CTRL">
-IO_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CTRL">
-IO_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CTRL">
-IO_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CTRL">
-IO_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CTRL">
-IO_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_LOCK">
-SLCR_LOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_pll_init_data_3_0">ps7_pll_init_data_3_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>SLCR SETTINGS</H1>
-<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_UNLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNLOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_UNLOCK@0XF8000008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>PLL SLCR REGISTERS</H1>
-<H1>ARM PLL INIT</H1>
-<H2><a name="ARM_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CFG</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CFG</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000110</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_CP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_CNT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>177</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>177000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CFG@0XF8000110</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffff0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1772c0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Configuration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>UPDATE FB_DIV</H1>
-<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_FDIV</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1a</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1a000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CTRL@0XF8000100</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1a000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>BY PASS PLL</H1>
-<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CTRL@0XF8000100</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ASSERT RESET</H1>
-<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CTRL@0XF8000100</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DEASSERT RESET</H1>
-<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CTRL@0XF8000100</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>CHECK PLL STATUS</H1>
-<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_STATUS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800010C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL lock status: 0: not locked, 1: locked</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PLL_STATUS@0XF800010C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>tobe</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>REMOVE PLL BY PASS</H1>
-<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CTRL@0XF8000100</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ARM_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000120</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Frequency divisor for the CPU clock source.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CPU_6OR4XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CPU_6x4x Clock control: 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CPU_3OR2XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:25</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CPU_3x2x Clock control: 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CPU_2XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:26</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CPU_2x Clock control: 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CPU_1x Clock control: 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CPU_PERI_CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>28:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock active: 0: Clock is disabled 1: Clock is enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_CLK_CTRL@0XF8000120</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1f003f30</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1f000200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>CPU Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DDR PLL INIT</H1>
-<H2><a name="DDR_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CFG</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CFG</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000114</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_CP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_CNT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1db</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1db000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CFG@0XF8000114</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffff0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1db2c0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Configuration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>UPDATE FB_DIV</H1>
-<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_FDIV</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>15</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CTRL@0XF8000104</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>15000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>BY PASS PLL</H1>
-<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CTRL@0XF8000104</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ASSERT RESET</H1>
-<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CTRL@0XF8000104</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DEASSERT RESET</H1>
-<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CTRL@0XF8000104</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>CHECK PLL STATUS</H1>
-<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_STATUS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800010C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL lock status: 0: not locked, 1: locked</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PLL_STATUS@0XF800010C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>tobe</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>REMOVE PLL BY PASS</H1>
-<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CTRL@0XF8000104</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDR_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000124</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_3XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR_3x Clock control: 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_2XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR_2x Clock control: 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_3XCLK_DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Frequency divisor for the ddr_3x clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_2XCLK_DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:26</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fc000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Frequency divisor for the ddr_2x clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_CLK_CTRL@0XF8000124</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff00003</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>c200003</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>IO PLL INIT</H1>
-<H2><a name="IO_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CFG</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CFG</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000118</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_CP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_CNT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1f4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CFG@0XF8000118</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffff0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1f42c0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Configuration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>UPDATE FB_DIV</H1>
-<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_FDIV</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>14</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CTRL@0XF8000108</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>14000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>BY PASS PLL</H1>
-<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CTRL@0XF8000108</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ASSERT RESET</H1>
-<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CTRL@0XF8000108</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DEASSERT RESET</H1>
-<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CTRL@0XF8000108</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>CHECK PLL STATUS</H1>
-<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_STATUS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800010C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL lock status: 0: not locked, 1: locked</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PLL_STATUS@0XF800010C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>tobe</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>REMOVE PLL BY PASS</H1>
-<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CTRL@0XF8000108</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>LOCK IT BACK</H1>
-<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_LOCK@0XF8000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-</TABLE>
-<P>
-<H2><a name="ps7_clock_init_data_3_0">ps7_clock_init_data_3_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_UNLOCK">
-SLCR_UNLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DCI_CLK_CTRL">
-DCI_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000128</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI clock control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#GEM0_RCLK_CTRL">
-GEM0_RCLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000138</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>GigE 0 Rx Clock and Rx Signals Select</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#GEM0_CLK_CTRL">
-GEM0_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000140</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>GigE 0 Ref Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LQSPI_CLK_CTRL">
-LQSPI_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800014C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Quad SPI Ref Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SDIO_CLK_CTRL">
-SDIO_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000150</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO Ref Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#UART_CLK_CTRL">
-UART_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000154</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART Ref Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#PCAP_CLK_CTRL">
-PCAP_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000168</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PCAP Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#FPGA0_CLK_CTRL">
-FPGA0_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000170</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PL Clock 0 Output control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CLK_621_TRUE">
-CLK_621_TRUE
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80001C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CPU Clock Ratio Mode select</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#APER_CLK_CTRL">
-APER_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800012C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AMBA Peripheral Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_LOCK">
-SLCR_LOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_clock_init_data_3_0">ps7_clock_init_data_3_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>SLCR SETTINGS</H1>
-<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_UNLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNLOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_UNLOCK@0XF8000008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>CLOCK CONTROL SLCR REGISTERS</H1>
-<H2><a name="DCI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DCI_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000128</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI clock control - 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>34</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3400</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DCI_CLK_CTRL@0XF8000128</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f03f01</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>203401</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DCI clock control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="GEM0_RCLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_RCLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GEM0_RCLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000138</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ethernet Controler 0 Rx Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>GEM0_RCLK_CTRL@0XF8000138</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>11</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>GigE 0 Rx Clock and Rx Signals Select</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="GEM0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GEM0_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000140</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ethernet Controller 0 Reference Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>First divisor for Ethernet controller 0 source clock.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Second divisor for Ethernet controller 0 source clock.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>GEM0_CLK_CTRL@0XF8000140</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f03f71</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>100801</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>GigE 0 Ref Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="LQSPI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)LQSPI_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LQSPI_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800014C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Quad SPI Controller Reference Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>500</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Divisor for Quad SPI Controller source clock.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LQSPI_CLK_CTRL@0XF800014C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f31</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>501</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Quad SPI Ref Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="SDIO_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)SDIO_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SDIO_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000150</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO Controller 0 Clock control. 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO Controller 1 Clock control. 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>14</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1400</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SDIO_CLK_CTRL@0XF8000150</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f33</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1401</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SDIO Ref Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="UART_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)UART_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UART_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000154</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART 0 Reference clock control. 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>a</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>a00</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Divisor for UART Controller source clock.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>UART_CLK_CTRL@0XF8000154</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f33</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>a03</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>UART Ref Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>TRACE CLOCK</H1>
-<H2><a name="PCAP_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)PCAP_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PCAP_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000168</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock active: 0: Clock is disabled 1: Clock is enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>500</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PCAP_CLK_CTRL@0XF8000168</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f31</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>501</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PCAP Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="FPGA0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA0_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA0_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000170</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>500</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>FPGA0_CLK_CTRL@0XF8000170</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f03f30</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200500</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PL Clock 0 Output control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CLK_621_TRUE">Register (<A href=#mod___slcr> slcr </A>)CLK_621_TRUE</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLK_621_TRUE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80001C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLK_621_TRUE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CLK_621_TRUE@0XF80001C4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>CPU Clock Ratio Mode select</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="APER_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)APER_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>APER_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800012C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DMA_CPU_2XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DMA controller AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>USB0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>USB controller 0 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>USB1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>USB controller 1 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GEM0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GEM1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SDI0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO controller 0 AMBA Clock 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SDI1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO controller 1 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SPI0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SPI 0 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SPI1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SPI 1 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CAN0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CAN 0 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CAN1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CAN 1 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>I2C0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>I2C 0 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>I2C1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>I2C 1 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UART0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART 0 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UART1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART 1 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GPIO_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>400000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>GPIO AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LQSPI_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:23</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Quad SPI AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SMC_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SMC AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>APER_CLK_CTRL@0XF800012C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ffcccd</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1fc044d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AMBA Peripheral Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>THIS SHOULD BE BLANK</H1>
-<H1>LOCK IT BACK</H1>
-<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_LOCK@0XF8000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-</TABLE>
-<P>
-<H2><a name="ps7_ddr_init_data_3_0">ps7_ddr_init_data_3_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ddrc_ctrl">
-ddrc_ctrl
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRC Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Two_rank_cfg">
-Two_rank_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Two Rank Configuration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#HPR_reg">
-HPR_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>HPR Queue control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LPR_reg">
-LPR_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800600C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>LPR Queue control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#WR_reg">
-WR_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006010</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>WR Queue control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_param_reg0">
-DRAM_param_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006014</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Parameters 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_param_reg1">
-DRAM_param_reg1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Parameters 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_param_reg2">
-DRAM_param_reg2
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800601C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Parameters 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_param_reg3">
-DRAM_param_reg3
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006020</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Parameters 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_param_reg4">
-DRAM_param_reg4
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006024</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Parameters 4</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_init_param">
-DRAM_init_param
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006028</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Initialization Parameters</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_EMR_reg">
-DRAM_EMR_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800602C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM EMR2, EMR3 access</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_EMR_MR_reg">
-DRAM_EMR_MR_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006030</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM EMR, MR access</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_burst8_rdwr">
-DRAM_burst8_rdwr
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Burst 8 read/write</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_disable_DQ">
-DRAM_disable_DQ
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006038</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Disable DQ</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_addr_map_bank">
-DRAM_addr_map_bank
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800603C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Row/Column address bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_addr_map_col">
-DRAM_addr_map_col
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006040</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Column address bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_addr_map_row">
-DRAM_addr_map_row
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006044</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select DRAM row address bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_ODT_reg">
-DRAM_ODT_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006048</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM ODT control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_cmd_timeout_rddata_cpt">
-phy_cmd_timeout_rddata_cpt
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006050</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY command time out and read data capture FIFO</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DLL_calib">
-DLL_calib
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006058</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DLL calibration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ODT_delay_hold">
-ODT_delay_hold
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800605C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ODT delay and ODT hold</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ctrl_reg1">
-ctrl_reg1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006060</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ctrl_reg2">
-ctrl_reg2
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006064</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ctrl_reg3">
-ctrl_reg3
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006068</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ctrl_reg4">
-ctrl_reg4
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800606C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller 4</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ctrl_reg5">
-ctrl_reg5
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006078</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller register 5</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ctrl_reg6">
-ctrl_reg6
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800607C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller register 6</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_T_ZQ">
-CHE_T_ZQ
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060A4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ZQ parameters</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_T_ZQ_Short_Interval_Reg">
-CHE_T_ZQ_Short_Interval_Reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Misc parameters</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#deep_pwrdwn_reg">
-deep_pwrdwn_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Deep powerdown (LPDDR2)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#reg_2c">
-reg_2c
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Training control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#reg_2d">
-reg_2d
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Misc Debug</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#dfi_timing">
-dfi_timing
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DFI timing</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_ECC_CONTROL_REG_OFFSET">
-CHE_ECC_CONTROL_REG_OFFSET
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ECC error clear</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_CORR_ECC_LOG_REG_OFFSET">
-CHE_CORR_ECC_LOG_REG_OFFSET
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060C8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ECC error correction</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_UNCORR_ECC_LOG_REG_OFFSET">
-CHE_UNCORR_ECC_LOG_REG_OFFSET
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060DC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ECC unrecoverable error status</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_ECC_STATS_REG_OFFSET">
-CHE_ECC_STATS_REG_OFFSET
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060F0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ECC error count</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ECC_scrub">
-ECC_scrub
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060F4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ECC mode/scrub</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_rcvr_enable">
-phy_rcvr_enable
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006114</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Phy receiver enable register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#PHY_Config">
-PHY_Config
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006118</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#PHY_Config">
-PHY_Config
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800611C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#PHY_Config">
-PHY_Config
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006120</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#PHY_Config">
-PHY_Config
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006124</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_init_ratio">
-phy_init_ratio
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800612C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_init_ratio">
-phy_init_ratio
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006130</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_init_ratio">
-phy_init_ratio
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006134</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_init_ratio">
-phy_init_ratio
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006138</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_rd_dqs_cfg">
-phy_rd_dqs_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006140</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_rd_dqs_cfg">
-phy_rd_dqs_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006144</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_rd_dqs_cfg">
-phy_rd_dqs_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006148</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_rd_dqs_cfg">
-phy_rd_dqs_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800614C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_wr_dqs_cfg">
-phy_wr_dqs_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006154</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_wr_dqs_cfg">
-phy_wr_dqs_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006158</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_wr_dqs_cfg">
-phy_wr_dqs_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800615C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_wr_dqs_cfg">
-phy_wr_dqs_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006160</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_we_cfg">
-phy_we_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006168</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY FIFO write enable configuration for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_we_cfg">
-phy_we_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800616C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY FIFO write enable configuration for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_we_cfg">
-phy_we_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006170</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY FIFO write enable configuration for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_we_cfg">
-phy_we_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006174</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY FIFO write enable configuration for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#wr_data_slv">
-wr_data_slv
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800617C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write data slave ratio config for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#wr_data_slv">
-wr_data_slv
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006180</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write data slave ratio config for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#wr_data_slv">
-wr_data_slv
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006184</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write data slave ratio config for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#wr_data_slv">
-wr_data_slv
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006188</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write data slave ratio config for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#reg_64">
-reg_64
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006190</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Training control 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#reg_65">
-reg_65
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006194</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Training control 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#page_mask">
-page_mask
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006204</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Page mask</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_wr_port">
-axi_priority_wr_port
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006208</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_wr_port">
-axi_priority_wr_port
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800620C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_wr_port">
-axi_priority_wr_port
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006210</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_wr_port">
-axi_priority_wr_port
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006214</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_rd_port">
-axi_priority_rd_port
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006218</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_rd_port">
-axi_priority_rd_port
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800621C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_rd_port">
-axi_priority_rd_port
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006220</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_rd_port">
-axi_priority_rd_port
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006224</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#lpddr_ctrl0">
-lpddr_ctrl0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>LPDDR2 Control 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#lpddr_ctrl1">
-lpddr_ctrl1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>LPDDR2 Control 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#lpddr_ctrl2">
-lpddr_ctrl2
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>LPDDR2 Control 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#lpddr_ctrl3">
-lpddr_ctrl3
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>LPDDR2 Control 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ddrc_ctrl">
-ddrc_ctrl
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRC Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_ddr_init_data_3_0">ps7_ddr_init_data_3_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>DDR INITIALIZATION</H1>
-<H1>LOCK DDR</H1>
-<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_ctrl</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_soft_rstb</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_powerdown_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_data_bus_width</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_burst8_refresh</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rdwr_idle_gap</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_rd_bypass</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_act_bypass</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_auto_refresh</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ddrc_ctrl@0XF8006000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRC Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Two_rank_cfg">Register (<A href=#mod___slcr> slcr </A>)Two_rank_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Two_rank_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rfc_nom_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_reg_ddrc_active_ranks</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_cs_bit0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Two_rank_cfg@0XF8006004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>107f</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Two Rank Configuration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="HPR_reg">Register (<A href=#mod___slcr> slcr </A>)HPR_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>HPR_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_hpr_min_non_critical_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks).</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_hpr_max_starve_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_hpr_xact_run_length</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3c00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3c00000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>HPR_reg@0XF8006008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3c0780f</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>HPR Queue control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="LPR_reg">Register (<A href=#mod___slcr> slcr </A>)LPR_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LPR_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800600C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_lpr_min_non_critical_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_lpr_max_starve_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_lpr_xact_run_length</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3c00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LPR_reg@0XF800600C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2001001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>LPR Queue control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="WR_reg">Register (<A href=#mod___slcr> slcr </A>)WR_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>WR_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006010</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_w_min_non_critical_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of clock cycles that the WR queue is guaranteed to be non-critical.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_w_xact_run_length</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_w_max_starve_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>WR_reg@0XF8006010</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>14001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>WR Queue control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_param_reg0">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_param_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006014</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rc</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1a</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1a</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rfc_min</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3fc0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>54</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1500</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_post_selfref_gap_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1fc000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_param_reg0@0XF8006014</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>4151a</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Parameters 0</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_param_reg1">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_param_reg1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_wr2pre</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>12</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_powerdown_to_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_faw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>15</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5400</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ras_max</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>23</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>230000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ras_min</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>13</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4c00000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_cke</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_param_reg1@0XF8006018</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f7ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>44e354d2</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Parameters 1</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_param_reg2">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg2</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_param_reg2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800601C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_write_latency</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rd2wr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_wr2rd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_xp</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tXP: Minimum time after power down exit to any operation. DRAM related.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_pad_pd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>700000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rd2pre</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:23</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f800000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rcd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>70000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_param_reg2@0XF800601C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>720238e5</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Parameters 2</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_param_reg3">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg3</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_param_reg3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006020</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ccd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rrd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_refresh_margin</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rp</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRP - Minimum time from precharge to activate of same bank. DRAM RELATED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_refresh_to_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mobile</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: DDR2 or DDR3 device. 1: LPDDR2 device.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_en_dfi_dram_clk_disable</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:23</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_read_latency</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>28:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_mode_ddr1_ddr2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>29:29</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_pad_pd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: disable the pad power down feature 0: Enable the pad power down feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_param_reg3@0XF8006020</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7fdffffc</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>270872d0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Parameters 3</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_param_reg4">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg4</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_param_reg4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006024</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_en_2t_timing_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: DDRC will use 2T timing 0: DDRC will use 1T timing</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_prefer_write</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: Bank selector prefers writes over reads</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr_wr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr_addr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr_data</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1fffe00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0].</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_reg_mr_wr_busy</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:25</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr_type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:26</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Indicates whether the Mode register operation is read or write 0: write 1: read</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr_rdata_valid</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_param_reg4@0XF8006024</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffffc3</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Parameters 4</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_init_param">Register (<A href=#mod___slcr> slcr </A>)DRAM_init_param</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_init_param</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006028</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_final_wait_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_pre_ocd_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>780</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_mrd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_init_param@0XF8006028</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2007</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Initialization Parameters</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_EMR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_EMR_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800602C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_emr2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_emr3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_EMR_reg@0XF800602C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM EMR2, EMR3 access</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_EMR_MR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_MR_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_EMR_MR_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006030</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>930</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>930</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_emr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_EMR_MR_reg@0XF8006030</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>40930</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM EMR, MR access</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_burst8_rdwr">Register (<A href=#mod___slcr> slcr </A>)DRAM_burst8_rdwr</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_burst8_rdwr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_burst_rdwr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_pre_cke_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>167</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1670</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_post_cke_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_burstchop</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>28:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Feature not supported. When 1, Controller is out in burstchop mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_burst8_rdwr@0XF8006034</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>13ff3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>11674</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Burst 8 read/write</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_disable_DQ">Register (<A href=#mod___slcr> slcr </A>)DRAM_disable_DQ</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_disable_DQ</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006038</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_force_low_pri_n</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_dq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_disable_DQ@0XF8006038</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Disable DQ</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_addr_map_bank">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_bank</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_addr_map_bank</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800603C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_bank_b0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_bank_b1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>70</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_bank_b2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>700</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_addr_map_bank@0XF800603C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>777</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Row/Column address bits</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_addr_map_col">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_col</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_addr_map_col</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006040</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b9</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f00000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b10</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b11</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f0000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_addr_map_col@0XF8006040</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>fff00000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Column address bits</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_addr_map_row">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_row</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_addr_map_row</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006044</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b2_11</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b12</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b13</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b14</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f00000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b15</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_addr_map_row@0XF8006044</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ff66666</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Select DRAM row address bits</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_ODT_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_ODT_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_ODT_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006048</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_local_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_local_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_idle_local_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_reg_ddrc_rank0_wr_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>38</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_reg_ddrc_rank0_rd_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_ODT_reg@0XF8006048</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f03f</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3c008</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM ODT control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_cmd_timeout_rddata_cpt">Register (<A href=#mod___slcr> slcr </A>)phy_cmd_timeout_rddata_cpt</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_cmd_timeout_rddata_cpt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006050</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_cmd_to_data</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Not used in DFI PHY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_cmd_to_data</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Not used in DFI PHY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdc_we_to_re_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdc_fifo_rst_disable</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_use_fixed_re</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdc_fifo_rst_err_cnt_clr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dis_phy_ctrl_rstn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_clk_stall_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: stall clock, for DLL aging control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_num_of_dq0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_num_of_dq0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>70000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_cmd_timeout_rddata_cpt@0XF8006050</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff0f8fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>77010800</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY command time out and read data capture FIFO</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DLL_calib">Register (<A href=#mod___slcr> slcr </A>)DLL_calib</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DLL_calib</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006058</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_dll_calib</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DLL_calib@0XF8006058</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DLL calibration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ODT_delay_hold">Register (<A href=#mod___slcr> slcr </A>)ODT_delay_hold</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ODT_delay_hold</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800605C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rd_odt_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UNUSED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_wr_odt_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rd_odt_hold</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_wr_odt_hold</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ODT_delay_hold@0XF800605C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>5003</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ODT delay and ODT hold</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ctrl_reg1">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ctrl_reg1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006060</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_pageclose</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_lpr_num_entries</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7e</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3e</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_auto_pre_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_refresh_update_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_wc</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable Write Combine: 0: enable 1: disable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_collision_page_opt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_selfref_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ctrl_reg1@0XF8006060</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>17ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3e</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Controller 1</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ctrl_reg2">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg2</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ctrl_reg2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006064</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_go2critical_hysteresis</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1fe0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_go2critical_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ctrl_reg2@0XF8006064</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>21fe0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>20000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Controller 2</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ctrl_reg3">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg3</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ctrl_reg3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006068</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_wrlvl_ww</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>41</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>41</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rdlvl_rr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>41</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_wlmrd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>28</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>280000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ctrl_reg3@0XF8006068</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>284141</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Controller 3</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ctrl_reg4">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg4</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ctrl_reg4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800606C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dfi_t_ctrlupd_interval_min_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dfi_t_ctrlupd_interval_max_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>16</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ctrl_reg4@0XF800606C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1610</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Controller 4</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ctrl_reg5">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg5</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ctrl_reg5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006078</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_ctrl_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_dram_clk_disable</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_dram_clk_enable</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_cksre</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_cksrx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ckesr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>400000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ctrl_reg5@0XF8006078</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>466111</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Controller register 5</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ctrl_reg6">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg6</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ctrl_reg6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800607C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ckpde</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ckpdx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ckdpde</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ckdpdx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ckcsx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ctrl_reg6@0XF800607C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>32222</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Controller register 6</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_T_ZQ">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_T_ZQ</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060A4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_auto_zq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_ddr3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_mod</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Mode register set command update delay (minimum d'128)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_zq_long_nop</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_zq_short_nop</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_T_ZQ@0XF80060A4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>10200802</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ZQ parameters</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_T_ZQ_Short_Interval_Reg">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ_Short_Interval_Reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_T_ZQ_Short_Interval_Reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>t_zq_short_interval_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c845</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c845</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dram_rstn_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>67</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6700000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_T_ZQ_Short_Interval_Reg@0XF80060A8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>670c845</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Misc parameters</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="deep_pwrdwn_reg">Register (<A href=#mod___slcr> slcr </A>)deep_pwrdwn_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>deep_pwrdwn_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>deeppowerdown_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>deeppowerdown_to_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1fe</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1fe</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>deep_pwrdwn_reg@0XF80060AC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1fe</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Deep powerdown (LPDDR2)</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="reg_2c">Register (<A href=#mod___slcr> slcr </A>)reg_2c</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_2c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dfi_wrlvl_max_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>fff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dfi_rdlvl_max_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>fff000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_reg_twrlvl_max_error</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_reg_trdlvl_max_error</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:25</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_wr_level_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:26</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_rd_dqs_gate_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_rd_data_eye_train</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>28:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>reg_2c@0XF80060B0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1cffffff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Training control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="reg_2d">Register (<A href=#mod___slcr> slcr </A>)reg_2d</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_2d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_skip_ocd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>reg_2d@0XF80060B4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Misc Debug</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="dfi_timing">Register (<A href=#mod___slcr> slcr </A>)dfi_timing</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dfi_timing</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_rddata_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_ctrlup_min</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7fe0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_ctrlup_max</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>dfi_timing@0XF80060B8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200066</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DFI timing</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_ECC_CONTROL_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_CONTROL_REG_OFFSET</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_ECC_CONTROL_REG_OFFSET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Clear_Uncorrectable_DRAM_ECC_error</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Clear_Correctable_DRAM_ECC_error</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ECC error clear</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_CORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_CORR_ECC_LOG_REG_OFFSET</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_CORR_ECC_LOG_REG_OFFSET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060C8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CORR_ECC_LOG_VALID</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ECC_CORRECTED_BIT_NUM</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fe</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ECC error correction</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_UNCORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_UNCORR_ECC_LOG_REG_OFFSET</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_UNCORR_ECC_LOG_REG_OFFSET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060DC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNCORR_ECC_LOG_VALID</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31).</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ECC unrecoverable error status</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_ECC_STATS_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_STATS_REG_OFFSET</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_ECC_STATS_REG_OFFSET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060F0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STAT_NUM_CORR_ERR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58).</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STAT_NUM_UNCORR_ERR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58).</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_ECC_STATS_REG_OFFSET@0XF80060F0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ECC error count</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ECC_scrub">Register (<A href=#mod___slcr> slcr </A>)ECC_scrub</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ECC_scrub</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060F4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_ecc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_scrub</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ECC_scrub@0XF80060F4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ECC mode/scrub</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_rcvr_enable">Register (<A href=#mod___slcr> slcr </A>)phy_rcvr_enable</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_rcvr_enable</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006114</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dif_on</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dif_off</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_rcvr_enable@0XF8006114</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Phy receiver enable register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PHY_Config</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006118</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_data_slice_in_use</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_shift_dq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7fc0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_err_clr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dq_offset</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PHY_Config@0XF8006118</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7fffffcf</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>40000001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PHY_Config</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800611C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_data_slice_in_use</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_shift_dq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7fc0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_err_clr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dq_offset</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PHY_Config@0XF800611C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7fffffcf</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>40000001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PHY_Config</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006120</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_data_slice_in_use</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_shift_dq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7fc0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_err_clr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dq_offset</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PHY_Config@0XF8006120</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7fffffcf</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>40000001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PHY_Config</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006124</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_data_slice_in_use</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_shift_dq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7fc0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_err_clr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dq_offset</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PHY_Config@0XF8006124</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7fffffcf</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>40000001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800612C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used by Write Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23c00</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used Gate Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_init_ratio@0XF800612C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>23c00</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006130</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used by Write Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8a</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used Gate Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_init_ratio@0XF8006130</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>22800</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006134</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used by Write Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22c00</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used Gate Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_init_ratio@0XF8006134</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>22c00</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006138</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used by Write Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>92</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used Gate Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_init_ratio@0XF8006138</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>24800</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_rd_dqs_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006140</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_rd_dqs_cfg@0XF8006140</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_rd_dqs_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006144</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_rd_dqs_cfg@0XF8006144</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_rd_dqs_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006148</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_rd_dqs_cfg@0XF8006148</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_rd_dqs_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800614C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_rd_dqs_cfg@0XF800614C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_wr_dqs_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006154</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>77</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>77</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_wr_dqs_cfg@0XF8006154</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>77</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_wr_dqs_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006158</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_wr_dqs_cfg@0XF8006158</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_wr_dqs_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800615C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_wr_dqs_cfg@0XF800615C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_wr_dqs_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006160</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>75</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>75</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_wr_dqs_cfg@0XF8006160</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>75</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_we_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006168</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Delay value to be used when reg_phy_fifo_we_in_force is set to 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_we_cfg@0XF8006168</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>e4</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY FIFO write enable configuration for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_we_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800616C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Delay value to be used when reg_phy_fifo_we_in_force is set to 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_we_cfg@0XF800616C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY FIFO write enable configuration for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_we_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006170</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Delay value to be used when reg_phy_fifo_we_in_force is set to 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_we_cfg@0XF8006170</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>e0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY FIFO write enable configuration for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_we_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006174</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e7</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Delay value to be used when reg_phy_fifo_we_in_force is set to 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_we_cfg@0XF8006174</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>e7</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY FIFO write enable configuration for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>wr_data_slv</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800617C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>b7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>b7</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>wr_data_slv@0XF800617C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>b7</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write data slave ratio config for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>wr_data_slv</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006180</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>bc</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>bc</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>wr_data_slv@0XF8006180</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>bc</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write data slave ratio config for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>wr_data_slv</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006184</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>bc</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>bc</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>wr_data_slv@0XF8006184</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>bc</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write data slave ratio config for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>wr_data_slv</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006188</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>b5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>b5</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>wr_data_slv@0XF8006188</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>b5</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write data slave ratio config for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="reg_64">Register (<A href=#mod___slcr> slcr </A>)reg_64</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_64</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006190</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bl2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved for future Use.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_at_spd_atpg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_enable</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_force_err</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_invert_clkout</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_sel_logic</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_ctrl_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_ctrl_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_ctrl_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fe00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_lpddr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>29:29</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: DDR2 or DDR3. 1: LPDDR2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_cmd_latency</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If set to 1, command comes to phy_ctrl through a flop.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>reg_64@0XF8006190</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>6ffffefe</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>40080</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Training control 2</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="reg_65">Register (<A href=#mod___slcr> slcr </A>)reg_65</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_65</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006194</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_rl_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_rl_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dll_lock_diff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3c00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3c00</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_use_wr_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_use_rd_dqs_gate_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_use_rd_data_eye_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dis_calib_rst</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_ctrl_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>reg_65@0XF8006194</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1fc82</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Training control 3</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="page_mask">Register (<A href=#mod___slcr> slcr </A>)page_mask</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>page_mask</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006204</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_page_addr_mask</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>page_mask@0XF8006204</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Page mask</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_wr_port</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006208</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_wr_port@0XF8006208</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>703ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_wr_port</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800620C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_wr_port@0XF800620C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>703ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_wr_port</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006210</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_wr_port@0XF8006210</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>703ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_wr_port</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006214</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_wr_port@0XF8006214</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>703ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_rd_port</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006218</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_set_hpr_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable reads to be generated as HPR for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_rd_port@0XF8006218</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_rd_port</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800621C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_set_hpr_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable reads to be generated as HPR for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_rd_port@0XF800621C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_rd_port</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006220</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_set_hpr_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable reads to be generated as HPR for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_rd_port@0XF8006220</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_rd_port</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006224</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_set_hpr_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable reads to be generated as HPR for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_rd_port@0XF8006224</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="lpddr_ctrl0">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>lpddr_ctrl0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_lpddr2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: DDR2 or DDR3 in use. 1: LPDDR2 in Use.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_derate_enable</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr4_margin</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UNUSED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>lpddr_ctrl0@0XF80062A8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff5</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>LPDDR2 Control 0</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="lpddr_ctrl1">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>lpddr_ctrl1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr4_read_interval</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Interval between two MR4 reads, USED to derate the timing parameters.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>lpddr_ctrl1@0XF80062AC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>LPDDR2 Control 1</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="lpddr_ctrl2">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl2</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>lpddr_ctrl2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_min_stable_clock_x1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_idle_after_reset_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>12</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>120</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Idle time after the reset command, tINIT4. Units: 32 clock cycles.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_mrw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>lpddr_ctrl2@0XF80062B0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>5125</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>LPDDR2 Control 2</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="lpddr_ctrl3">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl3</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>lpddr_ctrl3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_max_auto_init_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>a6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>a6</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dev_zqinit_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>12</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>lpddr_ctrl3@0XF80062B4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>12a6</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>LPDDR2 Control 3</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>POLL ON DCI STATUS</H1>
-<H2><a name="DDRIOB_DCI_STATUS">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_STATUS</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DCI_STATUS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B74</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DONE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI done signal</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DCI_STATUS@0XF8000B74</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>tobe</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>UNLOCK DDR</H1>
-<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_ctrl</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_soft_rstb</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_powerdown_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_data_bus_width</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_burst8_refresh</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rdwr_idle_gap</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_rd_bypass</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_act_bypass</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_auto_refresh</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ddrc_ctrl@0XF8006000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>81</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRC Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>CHECK DDR STATUS</H1>
-<H2><a name="mode_sts_reg">Register (<A href=#mod___slcr> slcr </A>)mode_sts_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>mode_sts_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006054</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_reg_operating_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>mode_sts_reg@0XF8006054</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>tobe</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-</TABLE>
-<P>
-<H2><a name="ps7_mio_init_data_3_0">ps7_mio_init_data_3_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_UNLOCK">
-SLCR_UNLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#GPIOB_CTRL">
-GPIOB_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PS IO Buffer Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_ADDR0">
-DDRIOB_ADDR0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for A[14:0], CKE and DRST_B</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_ADDR1">
-DDRIOB_ADDR1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B44</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DATA0">
-DDRIOB_DATA0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B48</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for Data 15:0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DATA1">
-DDRIOB_DATA1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B4C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for Data 31:16</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DIFF0">
-DDRIOB_DIFF0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B50</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for DQS 1:0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DIFF1">
-DDRIOB_DIFF1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B54</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for DQS 3:2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_CLOCK">
-DDRIOB_CLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B58</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for Clock Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DRIVE_SLEW_ADDR">
-DDRIOB_DRIVE_SLEW_ADDR
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B5C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive and Slew controls for Address and Command pins of the DDR Interface</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DRIVE_SLEW_DATA">
-DDRIOB_DRIVE_SLEW_DATA
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive and Slew controls for DQ pins of the DDR Interface</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DRIVE_SLEW_DIFF">
-DDRIOB_DRIVE_SLEW_DIFF
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B64</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive and Slew controls for DQS pins of the DDR Interface</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DRIVE_SLEW_CLOCK">
-DDRIOB_DRIVE_SLEW_CLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B68</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive and Slew controls for Clock pins of the DDR Interface</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DDR_CTRL">
-DDRIOB_DDR_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B6C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Buffer Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DCI_CTRL">
-DDRIOB_DCI_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB DCI Config</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DCI_CTRL">
-DDRIOB_DCI_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB DCI Config</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DCI_CTRL">
-DDRIOB_DCI_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB DCI Config</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_00">
-MIO_PIN_00
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000700</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 0 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_01">
-MIO_PIN_01
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000704</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 1 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_02">
-MIO_PIN_02
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000708</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 2 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_03">
-MIO_PIN_03
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800070C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 3 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_04">
-MIO_PIN_04
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000710</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 4 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_05">
-MIO_PIN_05
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000714</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 5 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_06">
-MIO_PIN_06
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000718</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 6 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_07">
-MIO_PIN_07
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800071C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 7 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_08">
-MIO_PIN_08
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000720</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 8 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_09">
-MIO_PIN_09
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000724</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 9 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_10">
-MIO_PIN_10
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000728</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 10 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_11">
-MIO_PIN_11
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800072C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 11 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_12">
-MIO_PIN_12
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000730</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 12 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_13">
-MIO_PIN_13
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000734</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 13 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_14">
-MIO_PIN_14
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000738</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 14 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_15">
-MIO_PIN_15
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800073C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 15 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_16">
-MIO_PIN_16
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000740</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 16 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_17">
-MIO_PIN_17
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000744</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 17 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_18">
-MIO_PIN_18
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000748</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 18 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_19">
-MIO_PIN_19
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800074C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 19 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_20">
-MIO_PIN_20
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000750</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 20 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_21">
-MIO_PIN_21
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000754</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 21 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_22">
-MIO_PIN_22
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000758</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 22 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_23">
-MIO_PIN_23
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800075C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 23 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_24">
-MIO_PIN_24
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000760</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 24 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_25">
-MIO_PIN_25
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000764</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 25 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_26">
-MIO_PIN_26
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000768</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 26 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_27">
-MIO_PIN_27
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800076C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 27 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_28">
-MIO_PIN_28
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000770</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 28 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_29">
-MIO_PIN_29
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000774</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 29 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_30">
-MIO_PIN_30
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000778</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 30 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_31">
-MIO_PIN_31
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800077C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 31 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_32">
-MIO_PIN_32
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000780</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 32 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_33">
-MIO_PIN_33
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000784</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 33 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_34">
-MIO_PIN_34
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000788</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 34 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_35">
-MIO_PIN_35
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800078C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 35 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_36">
-MIO_PIN_36
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000790</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 36 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_37">
-MIO_PIN_37
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000794</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 37 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_38">
-MIO_PIN_38
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000798</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 38 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_39">
-MIO_PIN_39
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800079C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 39 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_40">
-MIO_PIN_40
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 40 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_41">
-MIO_PIN_41
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 41 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_42">
-MIO_PIN_42
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 42 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_43">
-MIO_PIN_43
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 43 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_44">
-MIO_PIN_44
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 44 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_45">
-MIO_PIN_45
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 45 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_46">
-MIO_PIN_46
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 46 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_47">
-MIO_PIN_47
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007BC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 47 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_48">
-MIO_PIN_48
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 48 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_49">
-MIO_PIN_49
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 49 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_50">
-MIO_PIN_50
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 50 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_51">
-MIO_PIN_51
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007CC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 51 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_52">
-MIO_PIN_52
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007D0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 52 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_53">
-MIO_PIN_53
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007D4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 53 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SD0_WP_CD_SEL">
-SD0_WP_CD_SEL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000830</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO 0 WP CD select</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_LOCK">
-SLCR_LOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_mio_init_data_3_0">ps7_mio_init_data_3_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>SLCR SETTINGS</H1>
-<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_UNLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNLOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_UNLOCK@0XF8000008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>OCM REMAPPING</H1>
-<H2><a name="GPIOB_CTRL">Register (<A href=#mod___slcr> slcr </A>)GPIOB_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GPIOB_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VREF_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables VREF internal generator</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VREF_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies GPIO VREF Selection 000 - VREF = Disabled 001 - VREF = 0.9V 010 - VREF = test only - 1.8V 100 - VREF = test only - 1.25V Other values reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>GPIOB_CTRL@0XF8000B00</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>71</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PS IO Buffer Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DDRIOB SETTINGS</H1>
-<H2><a name="DDRIOB_ADDR0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_ADDR0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE_B</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enable: 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enable: 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_ADDR0@0XF8000B40</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for A[14:0], CKE and DRST_B</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_ADDR1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_ADDR1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B44</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE_B</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enable: 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enable: 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_ADDR1@0XF8000B44</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DATA0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B48</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE_B</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enable: 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enable: 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DATA0@0XF8000B48</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>672</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for Data 15:0</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DATA1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B4C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE_B</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enable: 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enable: 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DATA1@0XF8000B4C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>672</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for Data 31:16</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DIFF0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B50</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE_B</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enable: 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enable: 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DIFF0@0XF8000B50</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>674</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for DQS 1:0</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DIFF1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B54</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE_B</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enable: 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enable: 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DIFF1@0XF8000B54</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>674</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for DQS 3:2</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_CLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_CLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B58</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE_B</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enable: 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enable: 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_CLOCK@0XF8000B58</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for Clock Output</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DRIVE_SLEW_ADDR">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_ADDR</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DRIVE_SLEW_ADDR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B5C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_DRIVE_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_DRIVE_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_SLEW_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_SLEW_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>180000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_GTL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_RTERM</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>18c61c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Drive and Slew controls for Address and Command pins of the DDR Interface</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DRIVE_SLEW_DATA">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DATA</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DRIVE_SLEW_DATA</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_DRIVE_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_DRIVE_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_SLEW_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_SLEW_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_GTL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_RTERM</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DRIVE_SLEW_DATA@0XF8000B60</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>f9861c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Drive and Slew controls for DQ pins of the DDR Interface</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DRIVE_SLEW_DIFF">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DIFF</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DRIVE_SLEW_DIFF</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B64</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_DRIVE_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_DRIVE_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_SLEW_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_SLEW_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_GTL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_RTERM</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>f9861c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Drive and Slew controls for DQS pins of the DDR Interface</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DRIVE_SLEW_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_CLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DRIVE_SLEW_CLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B68</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_DRIVE_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_DRIVE_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_SLEW_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_SLEW_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_GTL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_RTERM</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>f9861c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Drive and Slew controls for Clock pins of the DDR Interface</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DDR_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DDR_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DDR_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B6C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VREF_INT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables VREF internal generator</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VREF_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1e</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VREF_EXT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_VREF_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>REFIO_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_REFIO_TEST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_REFIO_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_DRST_B_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_CKE_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DDR_CTRL@0XF8000B6C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>260</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Buffer Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ASSERT RESET</H1>
-<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DCI_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>At least toggle once to initialize flops in DCI system</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB DCI Config</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DEASSERT RESET</H1>
-<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DCI_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>At least toggle once to initialize flops in DCI system</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_VRN_OUT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>21</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB DCI Config</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DCI_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>At least toggle once to initialize flops in DCI system</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_VRP_TRI</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_VRN_TRI</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_VRP_OUT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_VRN_OUT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>NREF_OPT1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Calibration. Use the values in the Calibration Table.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>NREF_OPT2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>700</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Calibration. Use the values in the Calibration Table.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>NREF_OPT4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Calibration. Use the values in the Calibration Table.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PREF_OPT1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Calibration. Use the values in the Calibration Table.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PREF_OPT2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Calibration. Use the values in the Calibration Table.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UPDATE_CONTROL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Mode. Use the values in the Calibration Table.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_INIT_COMPLETE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_TST_CLK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_TST_HLN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:23</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_TST_HLP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_TST_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:25</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_INT_DCI_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:26</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7feffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>823</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB DCI Config</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MIO PROGRAMMING</H1>
-<H2><a name="MIO_PIN_00">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_00</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_00</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000700</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high. 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables Pullup on IO Buffer pin 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_00@0XF8000700</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 0 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_01">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_01</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_01</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000704</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_01@0XF8000704</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 1 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_02">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_02</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_02</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000708</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_02@0XF8000708</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 2 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_03">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_03</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_03</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800070C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_03@0XF800070C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 3 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_04">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_04</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_04</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000710</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_04@0XF8000710</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 4 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_05">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_05</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_05</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000714</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_05@0XF8000714</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 5 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_06">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_06</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_06</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000718</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_06@0XF8000718</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 6 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_07">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_07</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_07</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800071C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_07@0XF800071C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 7 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_08">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_08</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_08</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000720</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_08@0XF8000720</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 8 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_09">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_09</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_09</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000724</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_09@0XF8000724</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 9 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_10">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_10</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_10</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000728</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_10@0XF8000728</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1640</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 10 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_11">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_11</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_11</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800072C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_11@0XF800072C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1640</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 11 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_12">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_12</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_12</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000730</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_12@0XF8000730</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1640</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 12 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_13">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_13</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_13</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000734</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_13@0XF8000734</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1640</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 13 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_14">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_14</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_14</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000738</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_14@0XF8000738</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 14 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_15">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_15</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_15</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800073C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_15@0XF800073C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 15 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_16">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_16</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_16</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000740</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_16@0XF8000740</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 16 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_17">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_17</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_17</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000744</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_17@0XF8000744</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 17 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_18">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_18</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_18</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000748</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_18@0XF8000748</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 18 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_19">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_19</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_19</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800074C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_19@0XF800074C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 19 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_20">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_20</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_20</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000750</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_20@0XF8000750</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 20 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_21">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_21</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_21</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000754</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_21@0XF8000754</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 21 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_22">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_22</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_22</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000758</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_22@0XF8000758</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 22 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_23">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_23</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_23</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800075C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_23@0XF800075C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 23 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_24">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_24</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_24</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000760</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_24@0XF8000760</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 24 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_25">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_25</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_25</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000764</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_25@0XF8000764</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 25 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_26">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_26</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_26</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000768</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_26@0XF8000768</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 26 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_27">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_27</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_27</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800076C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_27@0XF800076C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 27 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_28">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_28</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_28</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000770</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_28@0XF8000770</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 28 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_29">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_29</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_29</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000774</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_29@0XF8000774</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>305</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 29 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_30">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_30</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_30</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000778</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_30@0XF8000778</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 30 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_31">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_31</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_31</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800077C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_31@0XF800077C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>305</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 31 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_32">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_32</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000780</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_32@0XF8000780</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 32 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_33">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_33</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_33</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000784</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_33@0XF8000784</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 33 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_34">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_34</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_34</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000788</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_34@0XF8000788</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 34 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_35">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_35</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_35</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800078C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_35@0XF800078C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 35 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_36">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_36</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_36</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000790</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_36@0XF8000790</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>305</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 36 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_37">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_37</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_37</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000794</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_37@0XF8000794</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 37 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_38">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_38</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_38</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000798</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_38@0XF8000798</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 38 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_39">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_39</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_39</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800079C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_39@0XF800079C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 39 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_40">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_40</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_40@0XF80007A0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 40 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_41">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_41</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_41</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_41@0XF80007A4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 41 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_42">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_42</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_42</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_42@0XF80007A8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 42 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_43">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_43</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_43</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_43@0XF80007AC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 43 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_44">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_44</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_44</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_44@0XF80007B0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 44 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_45">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_45</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_45</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_45@0XF80007B4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 45 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_46">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_46</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_46</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_46@0XF80007B8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 46 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_47">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_47</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_47</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007BC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_47@0XF80007BC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f01</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>201</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 47 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_48">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_48</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_48</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_48@0XF80007C0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2e0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 48 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_49">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_49</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_49</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_49@0XF80007C4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2e1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 49 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_50">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_50</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_50</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_50@0XF80007C8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 50 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_51">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_51</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_51</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007CC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_51@0XF80007CC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 51 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_52">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_52</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_52</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007D0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_52@0XF80007D0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 52 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_53">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_53</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_53</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007D4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULLUP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_53@0XF80007D4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 53 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="SD0_WP_CD_SEL">Register (<A href=#mod___slcr> slcr </A>)SD0_WP_CD_SEL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SD0_WP_CD_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000830</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SDIO0_WP_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>37</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>37</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SDIO0_CD_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2f0000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SD0_WP_CD_SEL@0XF8000830</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f003f</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2f0037</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SDIO 0 WP CD select</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>LOCK IT BACK</H1>
-<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_LOCK@0XF8000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-</TABLE>
-<P>
-<H2><a name="ps7_peripherals_init_data_3_0">ps7_peripherals_init_data_3_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_UNLOCK">
-SLCR_UNLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DATA0">
-DDRIOB_DATA0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B48</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for Data 15:0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DATA1">
-DDRIOB_DATA1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B4C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for Data 31:16</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DIFF0">
-DDRIOB_DIFF0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B50</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for DQS 1:0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DIFF1">
-DDRIOB_DIFF1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B54</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for DQS 3:2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_LOCK">
-SLCR_LOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Baud_rate_divider_reg0">
-Baud_rate_divider_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud Rate Divider Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Baud_rate_gen_reg0">
-Baud_rate_gen_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud Rate Generator Register.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Control_reg0">
-Control_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART Control Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#mode_reg0">
-mode_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART Mode Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Baud_rate_divider_reg0">
-Baud_rate_divider_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud Rate Divider Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Baud_rate_gen_reg0">
-Baud_rate_gen_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud Rate Generator Register.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Control_reg0">
-Control_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART Control Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#mode_reg0">
-mode_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART Mode Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Config_reg">
-Config_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000D000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SPI configuration register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CTRL">
-CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8007000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DIRM_1">
-DIRM_1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A244</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Direction mode (GPIO Bank1, MIO)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MASK_DATA_1_LSW">
-MASK_DATA_1_LSW
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#OEN_1">
-OEN_1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A248</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Output enable (GPIO Bank1, MIO)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MASK_DATA_1_LSW">
-MASK_DATA_1_LSW
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MASK_DATA_1_LSW">
-MASK_DATA_1_LSW
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_peripherals_init_data_3_0">ps7_peripherals_init_data_3_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>SLCR SETTINGS</H1>
-<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_UNLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNLOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_UNLOCK@0XF8000008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DDR TERM/IBUF_DISABLE_MODE SETTINGS</H1>
-<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DATA0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B48</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DATA0@0XF8000B48</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for Data 15:0</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DATA1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B4C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DATA1@0XF8000B4C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for Data 31:16</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DIFF0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B50</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DIFF0@0XF8000B50</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for DQS 1:0</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DIFF1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B54</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DIFF1@0XF8000B54</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for DQS 3:2</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>LOCK IT BACK</H1>
-<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_LOCK@0XF8000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>SRAM/NOR SET OPMODE</H1>
-<H1>UART REGISTERS</H1>
-<H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Baud_rate_divider_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>BDIV</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Baud_rate_divider_reg0@0XE0001034</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Baud Rate Divider Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Baud_rate_gen_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CD</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Baud_rate_gen_reg0@0XE0001018</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Baud Rate Generator Register.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Control_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STPBRK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STTBRK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RSTTO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXDIS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Transmit disable: 0: enable transmitter 1: disable transmitter</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXEN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXDIS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Receive disable: 0: enable 1: disable, regardless of the value of RXEN</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXEN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXRES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXRES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Control_reg0@0XE0001000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>17</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>UART Control Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>mode_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHMODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>300</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>NBSTOP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PAR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>38</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>mode_reg0@0XE0001004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>UART Mode Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Baud_rate_divider_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>BDIV</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Baud_rate_divider_reg0@0XE0000034</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Baud Rate Divider Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Baud_rate_gen_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CD</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Baud_rate_gen_reg0@0XE0000018</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Baud Rate Generator Register.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Control_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STPBRK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STTBRK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RSTTO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXDIS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Transmit disable: 0: enable transmitter 1: disable transmitter</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXEN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXDIS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Receive disable: 0: enable 1: disable, regardless of the value of RXEN</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXEN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXRES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXRES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Control_reg0@0XE0000000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>17</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>UART Control Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>mode_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHMODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>300</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>NBSTOP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PAR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>38</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>mode_reg0@0XE0000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>UART Mode Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>QSPI REGISTERS</H1>
-<H2><a name="Config_reg">Register (<A href=#mod___slcr> slcr </A>)Config_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Config_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000D000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Holdb_dr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Config_reg@0XE000D000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SPI configuration register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>PL POWER ON RESET REGISTERS</H1>
-<H2><a name="CTRL">Register (<A href=#mod___slcr> slcr </A>)CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8007000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PCFG_POR_CNT_4K</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>29:29</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CTRL@0XF8007000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>20000000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>SMC TIMING CALCULATION REGISTER UPDATE</H1>
-<H1>NAND SET CYCLE</H1>
-<H1>OPMODE</H1>
-<H1>DIRECT COMMAND</H1>
-<H1>SRAM/NOR CS0 SET CYCLE</H1>
-<H1>DIRECT COMMAND</H1>
-<H1>NOR CS0 BASE ADDRESS</H1>
-<H1>SRAM/NOR CS1 SET CYCLE</H1>
-<H1>DIRECT COMMAND</H1>
-<H1>NOR CS1 BASE ADDRESS</H1>
-<H1>USB RESET</H1>
-<H1>USB0 RESET</H1>
-<H1>DIR MODE BANK 0</H1>
-<H1>DIR MODE BANK 1</H1>
-<H2><a name="DIRM_1">Register (<A href=#mod___slcr> slcr </A>)DIRM_1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIRM_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A244</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIRECTION_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operation is the same as DIRM_0[DIRECTION_0]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DIRM_1@0XE000A244</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Direction mode (GPIO Bank1, MIO)</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>bfff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>bfff0000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MASK_DATA_1_LSW@0XE000A008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>bfff4000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE BANK 0</H1>
-<H1>OUTPUT ENABLE BANK 1</H1>
-<H2><a name="OEN_1">Register (<A href=#mod___slcr> slcr </A>)OEN_1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OEN_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A248</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OP_ENABLE_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operation is the same as OEN_0[OP_ENABLE_0]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>OEN_1@0XE000A248</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Output enable (GPIO Bank1, MIO)</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>bfff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>bfff0000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MASK_DATA_1_LSW@0XE000A008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>bfff0000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>bfff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>bfff0000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MASK_DATA_1_LSW@0XE000A008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>bfff4000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>USB1 RESET</H1>
-<H1>DIR MODE BANK 0</H1>
-<H1>DIR MODE BANK 1</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE BANK 0</H1>
-<H1>OUTPUT ENABLE BANK 1</H1>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>ENET RESET</H1>
-<H1>ENET0 RESET</H1>
-<H1>DIR MODE BANK 0</H1>
-<H1>DIR MODE BANK 1</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE BANK 0</H1>
-<H1>OUTPUT ENABLE BANK 1</H1>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>ENET1 RESET</H1>
-<H1>DIR MODE BANK 0</H1>
-<H1>DIR MODE BANK 1</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE BANK 0</H1>
-<H1>OUTPUT ENABLE BANK 1</H1>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>I2C RESET</H1>
-<H1>I2C0 RESET</H1>
-<H1>DIR MODE GPIO BANK0</H1>
-<H1>DIR MODE GPIO BANK1</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE</H1>
-<H1>OUTPUT ENABLE</H1>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>I2C1 RESET</H1>
-<H1>DIR MODE GPIO BANK0</H1>
-<H1>DIR MODE GPIO BANK1</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE</H1>
-<H1>OUTPUT ENABLE</H1>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>NOR CHIP SELECT</H1>
-<H1>DIR MODE BANK 0</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>OUTPUT ENABLE BANK 0</H1>
-</TABLE>
-<P>
-<H2><a name="ps7_post_config_3_0">ps7_post_config_3_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_UNLOCK">
-SLCR_UNLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LVL_SHFTR_EN">
-LVL_SHFTR_EN
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000900</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level Shifters Enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#FPGA_RST_CTRL">
-FPGA_RST_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000240</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA Software Reset Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_LOCK">
-SLCR_LOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_post_config_3_0">ps7_post_config_3_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>SLCR SETTINGS</H1>
-<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_UNLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNLOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_UNLOCK@0XF8000008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ENABLING LEVEL SHIFTER</H1>
-<H2><a name="LVL_SHFTR_EN">Register (<A href=#mod___slcr> slcr </A>)LVL_SHFTR_EN</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LVL_SHFTR_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000900</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>USER_LVL_INP_EN_0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level shifter enable to drive signals from PL to PS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>USER_LVL_OUT_EN_0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level shifter enable to drive signals from PS to PL</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>USER_LVL_INP_EN_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level shifter enable to drive signals from PL to PS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>USER_LVL_OUT_EN_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level shifter enable to drive signals from PS to PL</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LVL_SHFTR_EN@0XF8000900</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>f</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Level Shifters Enable</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>FPGA RESETS TO 0</H1>
-<H2><a name="FPGA_RST_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA_RST_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_RST_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000240</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:25</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fe000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Writes are ignored, read data is zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_FPGA_ACP_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_FPGA_AXDS3_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:23</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_FPGA_AXDS2_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_FPGA_AXDS1_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_FPGA_AXDS0_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Writes are ignored, read data is zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_FSSW1_FPGA_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_FSSW0_FPGA_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Writes are ignored, read data is zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_FPGA_FMSW1_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_FPGA_FMSW0_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_FPGA_DMA3_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_FPGA_DMA2_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_FPGA_DMA1_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_FPGA_DMA0_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Do not modify.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Writes are ignored, read data is zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA3_OUT_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA2_OUT_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA1_OUT_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA0_OUT_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>FPGA_RST_CTRL@0XF8000240</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>FPGA Software Reset Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>AFI REGISTERS</H1>
-<H1>AFI0 REGISTERS</H1>
-<H1>AFI1 REGISTERS</H1>
-<H1>AFI2 REGISTERS</H1>
-<H1>AFI3 REGISTERS</H1>
-<H1>AFI2 SECURE REGISTER</H1>
-<H1>LOCK IT BACK</H1>
-<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_LOCK@0XF8000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-</TABLE>
-<P>
-<H2><a name="ps7_debug_3_0">ps7_debug_3_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LAR">
-LAR
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8898FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LAR">
-LAR
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8899FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LAR">
-LAR
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8809FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_debug_3_0">ps7_debug_3_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>CROSS TRIGGER CONFIGURATIONS</H1>
-<H1>UNLOCKING CTI REGISTERS</H1>
-<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LAR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8898FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LAR@0XF8898FB0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LAR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8899FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LAR@0XF8899FB0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LAR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8809FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LAR@0XF8809FB0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ENABLING CTI MODULES AND CHANNELS</H1>
-<H1>MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS</H1>
-</TABLE>
-<P>
-</body>
-</head>
-</body>
-</html>
-<H2><a name="ps7_pll_init_data_2_0">ps7_pll_init_data_2_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_UNLOCK">
-SLCR_UNLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CFG">
-ARM_PLL_CFG
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000110</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Configuration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CTRL">
-ARM_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CTRL">
-ARM_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CTRL">
-ARM_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CTRL">
-ARM_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CTRL">
-ARM_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_CLK_CTRL">
-ARM_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000120</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CPU Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CFG">
-DDR_PLL_CFG
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000114</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Configuration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CTRL">
-DDR_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CTRL">
-DDR_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CTRL">
-DDR_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CTRL">
-DDR_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CTRL">
-DDR_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_CLK_CTRL">
-DDR_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000124</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CFG">
-IO_PLL_CFG
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000118</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Configuration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CTRL">
-IO_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CTRL">
-IO_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CTRL">
-IO_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CTRL">
-IO_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CTRL">
-IO_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_LOCK">
-SLCR_LOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_pll_init_data_2_0">ps7_pll_init_data_2_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>SLCR SETTINGS</H1>
-<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_UNLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNLOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_UNLOCK@0XF8000008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>PLL SLCR REGISTERS</H1>
-<H1>ARM PLL INIT</H1>
-<H2><a name="ARM_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CFG</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CFG</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000110</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_CP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_CNT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>177</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>177000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CFG@0XF8000110</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffff0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1772c0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Configuration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>UPDATE FB_DIV</H1>
-<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_FDIV</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1a</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1a000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CTRL@0XF8000100</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1a000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>BY PASS PLL</H1>
-<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CTRL@0XF8000100</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ASSERT RESET</H1>
-<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CTRL@0XF8000100</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DEASSERT RESET</H1>
-<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CTRL@0XF8000100</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>CHECK PLL STATUS</H1>
-<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_STATUS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800010C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL lock status: 0: not locked, 1: locked</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PLL_STATUS@0XF800010C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>tobe</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>REMOVE PLL BY PASS</H1>
-<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CTRL@0XF8000100</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ARM_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000120</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Frequency divisor for the CPU clock source.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CPU_6OR4XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CPU_6x4x Clock control: 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CPU_3OR2XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:25</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CPU_3x2x Clock control: 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CPU_2XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:26</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CPU_2x Clock control: 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CPU_1x Clock control: 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CPU_PERI_CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>28:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock active: 0: Clock is disabled 1: Clock is enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_CLK_CTRL@0XF8000120</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1f003f30</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1f000200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>CPU Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DDR PLL INIT</H1>
-<H2><a name="DDR_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CFG</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CFG</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000114</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_CP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_CNT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1db</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1db000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CFG@0XF8000114</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffff0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1db2c0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Configuration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>UPDATE FB_DIV</H1>
-<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_FDIV</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>15</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CTRL@0XF8000104</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>15000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>BY PASS PLL</H1>
-<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CTRL@0XF8000104</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ASSERT RESET</H1>
-<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CTRL@0XF8000104</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DEASSERT RESET</H1>
-<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CTRL@0XF8000104</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>CHECK PLL STATUS</H1>
-<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_STATUS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800010C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL lock status: 0: not locked, 1: locked</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PLL_STATUS@0XF800010C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>tobe</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>REMOVE PLL BY PASS</H1>
-<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CTRL@0XF8000104</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDR_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000124</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_3XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR_3x Clock control: 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_2XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR_2x Clock control: 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_3XCLK_DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Frequency divisor for the ddr_3x clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_2XCLK_DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:26</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fc000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Frequency divisor for the ddr_2x clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_CLK_CTRL@0XF8000124</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff00003</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>c200003</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>IO PLL INIT</H1>
-<H2><a name="IO_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CFG</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CFG</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000118</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_CP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_CNT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1f4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CFG@0XF8000118</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffff0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1f42c0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Configuration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>UPDATE FB_DIV</H1>
-<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_FDIV</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>14</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CTRL@0XF8000108</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>14000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>BY PASS PLL</H1>
-<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CTRL@0XF8000108</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ASSERT RESET</H1>
-<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CTRL@0XF8000108</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DEASSERT RESET</H1>
-<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CTRL@0XF8000108</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>CHECK PLL STATUS</H1>
-<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_STATUS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800010C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL lock status: 0: not locked, 1: locked</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PLL_STATUS@0XF800010C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>tobe</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>REMOVE PLL BY PASS</H1>
-<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CTRL@0XF8000108</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>LOCK IT BACK</H1>
-<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_LOCK@0XF8000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-</TABLE>
-<P>
-<H2><a name="ps7_clock_init_data_2_0">ps7_clock_init_data_2_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_UNLOCK">
-SLCR_UNLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DCI_CLK_CTRL">
-DCI_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000128</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI clock control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#GEM0_RCLK_CTRL">
-GEM0_RCLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000138</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>GigE 0 Rx Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#GEM0_CLK_CTRL">
-GEM0_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000140</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>GigE 0 Ref Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LQSPI_CLK_CTRL">
-LQSPI_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800014C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Quad SPI Ref Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SDIO_CLK_CTRL">
-SDIO_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000150</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO Ref Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#UART_CLK_CTRL">
-UART_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000154</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART Ref Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#PCAP_CLK_CTRL">
-PCAP_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000168</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PCAP Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#FPGA0_CLK_CTRL">
-FPGA0_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000170</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PL Clock 0 Output control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CLK_621_TRUE">
-CLK_621_TRUE
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80001C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CPU Clock Ratio Mode select</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#APER_CLK_CTRL">
-APER_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800012C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AMBA Peripheral Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_LOCK">
-SLCR_LOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_clock_init_data_2_0">ps7_clock_init_data_2_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>SLCR SETTINGS</H1>
-<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_UNLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNLOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_UNLOCK@0XF8000008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>CLOCK CONTROL SLCR REGISTERS</H1>
-<H2><a name="DCI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DCI_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000128</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI clock control - 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>34</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3400</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DCI_CLK_CTRL@0XF8000128</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f03f01</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>203401</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DCI clock control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="GEM0_RCLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_RCLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GEM0_RCLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000138</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ethernet Controler 0 Rx Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>GEM0_RCLK_CTRL@0XF8000138</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>11</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>GigE 0 Rx Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="GEM0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GEM0_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000140</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ethernet Controller 0 Reference Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>First divisor for Ethernet controller 0 source clock.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Second divisor for Ethernet controller 0 source clock.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>GEM0_CLK_CTRL@0XF8000140</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f03f71</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>100801</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>GigE 0 Ref Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="LQSPI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)LQSPI_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LQSPI_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800014C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Quad SPI Controller Reference Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>500</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Divisor for Quad SPI Controller source clock.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LQSPI_CLK_CTRL@0XF800014C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f31</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>501</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Quad SPI Ref Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="SDIO_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)SDIO_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SDIO_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000150</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO Controller 0 Clock control. 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO Controller 1 Clock control. 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>14</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1400</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SDIO_CLK_CTRL@0XF8000150</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f33</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1401</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SDIO Ref Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="UART_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)UART_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UART_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000154</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART 0 Reference clock control. 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>a</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>a00</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Divisor for UART Controller source clock.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>UART_CLK_CTRL@0XF8000154</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f33</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>a03</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>UART Ref Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>TRACE CLOCK</H1>
-<H2><a name="PCAP_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)PCAP_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PCAP_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000168</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock active: 0: Clock is disabled 1: Clock is enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>500</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PCAP_CLK_CTRL@0XF8000168</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f31</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>501</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PCAP Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="FPGA0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA0_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA0_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000170</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>500</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>FPGA0_CLK_CTRL@0XF8000170</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f03f30</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200500</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PL Clock 0 Output control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CLK_621_TRUE">Register (<A href=#mod___slcr> slcr </A>)CLK_621_TRUE</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLK_621_TRUE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80001C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLK_621_TRUE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select the CPU clock ration: 0: 4:2:1 1: 6:2:1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CLK_621_TRUE@0XF80001C4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>CPU Clock Ratio Mode select</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="APER_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)APER_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>APER_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800012C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DMA_CPU_2XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DMA controller AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>USB0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>USB controller 0 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>USB1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>USB controller 1 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GEM0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GEM1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SDI0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO controller 0 AMBA Clock 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SDI1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO controller 1 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SPI0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SPI 0 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SPI1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SPI 1 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CAN0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CAN 0 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CAN1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CAN 1 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>I2C0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>I2C 0 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>I2C1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>I2C 1 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UART0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART 0 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UART1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART 1 AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GPIO_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>400000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>GPIO AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LQSPI_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:23</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Quad SPI AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SMC_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SMC AMBA Clock control 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>APER_CLK_CTRL@0XF800012C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ffcccd</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1fc044d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AMBA Peripheral Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>THIS SHOULD BE BLANK</H1>
-<H1>LOCK IT BACK</H1>
-<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_LOCK@0XF8000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-</TABLE>
-<P>
-<H2><a name="ps7_ddr_init_data_2_0">ps7_ddr_init_data_2_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ddrc_ctrl">
-ddrc_ctrl
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRC Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Two_rank_cfg">
-Two_rank_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Two Rank Configuration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#HPR_reg">
-HPR_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>HPR Queue control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LPR_reg">
-LPR_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800600C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>LPR Queue control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#WR_reg">
-WR_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006010</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>WR Queue control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_param_reg0">
-DRAM_param_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006014</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Parameters 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_param_reg1">
-DRAM_param_reg1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Parameters 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_param_reg2">
-DRAM_param_reg2
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800601C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Parameters 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_param_reg3">
-DRAM_param_reg3
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006020</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Parameters 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_param_reg4">
-DRAM_param_reg4
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006024</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Parameters 4</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_init_param">
-DRAM_init_param
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006028</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Initialization Parameters</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_EMR_reg">
-DRAM_EMR_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800602C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM EMR2, EMR3 access</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_EMR_MR_reg">
-DRAM_EMR_MR_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006030</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM EMR, MR access</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_burst8_rdwr">
-DRAM_burst8_rdwr
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Burst 8 read/write</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_disable_DQ">
-DRAM_disable_DQ
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006038</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Disable DQ</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_addr_map_bank">
-DRAM_addr_map_bank
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800603C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Row/Column address bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_addr_map_col">
-DRAM_addr_map_col
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006040</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Column address bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_addr_map_row">
-DRAM_addr_map_row
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006044</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select DRAM row address bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_ODT_reg">
-DRAM_ODT_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006048</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM ODT control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_cmd_timeout_rddata_cpt">
-phy_cmd_timeout_rddata_cpt
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006050</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY command time out and read data capture FIFO</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DLL_calib">
-DLL_calib
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006058</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DLL calibration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ODT_delay_hold">
-ODT_delay_hold
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800605C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ODT delay and ODT hold</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ctrl_reg1">
-ctrl_reg1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006060</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ctrl_reg2">
-ctrl_reg2
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006064</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ctrl_reg3">
-ctrl_reg3
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006068</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ctrl_reg4">
-ctrl_reg4
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800606C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller 4</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ctrl_reg5">
-ctrl_reg5
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006078</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller register 5</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ctrl_reg6">
-ctrl_reg6
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800607C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller register 6</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_REFRESH_TIMER01">
-CHE_REFRESH_TIMER01
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060A0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CHE_REFRESH_TIMER01</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_T_ZQ">
-CHE_T_ZQ
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060A4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ZQ parameters</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_T_ZQ_Short_Interval_Reg">
-CHE_T_ZQ_Short_Interval_Reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Misc parameters</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#deep_pwrdwn_reg">
-deep_pwrdwn_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Deep powerdown (LPDDR2)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#reg_2c">
-reg_2c
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Training control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#reg_2d">
-reg_2d
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Misc Debug</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#dfi_timing">
-dfi_timing
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DFI timing</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_ECC_CONTROL_REG_OFFSET">
-CHE_ECC_CONTROL_REG_OFFSET
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ECC error clear</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_CORR_ECC_LOG_REG_OFFSET">
-CHE_CORR_ECC_LOG_REG_OFFSET
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060C8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ECC error correction</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_UNCORR_ECC_LOG_REG_OFFSET">
-CHE_UNCORR_ECC_LOG_REG_OFFSET
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060DC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ECC unrecoverable error status</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_ECC_STATS_REG_OFFSET">
-CHE_ECC_STATS_REG_OFFSET
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060F0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ECC error count</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ECC_scrub">
-ECC_scrub
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060F4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ECC mode/scrub</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_rcvr_enable">
-phy_rcvr_enable
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006114</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Phy receiver enable register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#PHY_Config0">
-PHY_Config0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006118</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#PHY_Config1">
-PHY_Config1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800611C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY configuration register for data slice 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#PHY_Config2">
-PHY_Config2
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006120</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY configuration register for data slice 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#PHY_Config3">
-PHY_Config3
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006124</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY configuration register for data slice 3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_init_ratio0">
-phy_init_ratio0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800612C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_init_ratio1">
-phy_init_ratio1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006130</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY init ratio register for data slice 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_init_ratio2">
-phy_init_ratio2
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006134</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY init ratio register for data slice 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_init_ratio3">
-phy_init_ratio3
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006138</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY init ratio register for data slice 3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_rd_dqs_cfg0">
-phy_rd_dqs_cfg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006140</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_rd_dqs_cfg1">
-phy_rd_dqs_cfg1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006144</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY read DQS configuration register for data slice 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_rd_dqs_cfg2">
-phy_rd_dqs_cfg2
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006148</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY read DQS configuration register for data slice 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_rd_dqs_cfg3">
-phy_rd_dqs_cfg3
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800614C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY read DQS configuration register for data slice 3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_wr_dqs_cfg0">
-phy_wr_dqs_cfg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006154</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_wr_dqs_cfg1">
-phy_wr_dqs_cfg1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006158</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write DQS configuration register for data slice 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_wr_dqs_cfg2">
-phy_wr_dqs_cfg2
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800615C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write DQS configuration register for data slice 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_wr_dqs_cfg3">
-phy_wr_dqs_cfg3
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006160</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write DQS configuration register for data slice 3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_we_cfg0">
-phy_we_cfg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006168</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY FIFO write enable configuration for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_we_cfg1">
-phy_we_cfg1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800616C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY FIFO write enable configuration for data slice 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_we_cfg2">
-phy_we_cfg2
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006170</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY FIFO write enable configuration for data slice 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_we_cfg3">
-phy_we_cfg3
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006174</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY FIFO write enable configuration for data slice 3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#wr_data_slv0">
-wr_data_slv0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800617C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write data slave ratio config for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#wr_data_slv1">
-wr_data_slv1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006180</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write data slave ratio config for data slice 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#wr_data_slv2">
-wr_data_slv2
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006184</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write data slave ratio config for data slice 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#wr_data_slv3">
-wr_data_slv3
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006188</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write data slave ratio config for data slice 3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#reg_64">
-reg_64
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006190</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Training control 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#reg_65">
-reg_65
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006194</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Training control 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#page_mask">
-page_mask
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006204</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Page mask</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_wr_port0">
-axi_priority_wr_port0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006208</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_wr_port1">
-axi_priority_wr_port1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800620C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for write port 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_wr_port2">
-axi_priority_wr_port2
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006210</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for write port 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_wr_port3">
-axi_priority_wr_port3
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006214</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for write port 3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_rd_port0">
-axi_priority_rd_port0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006218</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_rd_port1">
-axi_priority_rd_port1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800621C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for read port 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_rd_port2">
-axi_priority_rd_port2
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006220</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for read port 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_rd_port3">
-axi_priority_rd_port3
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006224</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for read port 3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#lpddr_ctrl0">
-lpddr_ctrl0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>LPDDR2 Control 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#lpddr_ctrl1">
-lpddr_ctrl1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>LPDDR2 Control 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#lpddr_ctrl2">
-lpddr_ctrl2
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>LPDDR2 Control 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#lpddr_ctrl3">
-lpddr_ctrl3
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>LPDDR2 Control 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ddrc_ctrl">
-ddrc_ctrl
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRC Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_ddr_init_data_2_0">ps7_ddr_init_data_2_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>DDR INITIALIZATION</H1>
-<H1>LOCK DDR</H1>
-<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_ctrl</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_soft_rstb</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_powerdown_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_data_bus_width</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_burst8_refresh</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rdwr_idle_gap</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_rd_bypass</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_act_bypass</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_auto_refresh</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ddrc_ctrl@0XF8006000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRC Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Two_rank_cfg">Register (<A href=#mod___slcr> slcr </A>)Two_rank_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Two_rank_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rfc_nom_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_active_ranks</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_cs_bit0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_wr_odt_block</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>180000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_diff_rank_rd_2cycle_gap</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_cs_bit1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_open_bank</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_4bank_ram</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>28:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Two_rank_cfg@0XF8006004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>8107f</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Two Rank Configuration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="HPR_reg">Register (<A href=#mod___slcr> slcr </A>)HPR_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>HPR_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_hpr_min_non_critical_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks).</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_hpr_max_starve_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_hpr_xact_run_length</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3c00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3c00000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>HPR_reg@0XF8006008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3c0780f</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>HPR Queue control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="LPR_reg">Register (<A href=#mod___slcr> slcr </A>)LPR_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LPR_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800600C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_lpr_min_non_critical_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_lpr_max_starve_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_lpr_xact_run_length</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3c00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LPR_reg@0XF800600C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2001001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>LPR Queue control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="WR_reg">Register (<A href=#mod___slcr> slcr </A>)WR_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>WR_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006010</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_w_min_non_critical_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of clock cycles that the WR queue is guaranteed to be non-critical.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_w_xact_run_length</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_w_max_starve_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>WR_reg@0XF8006010</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>14001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>WR Queue control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_param_reg0">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_param_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006014</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rc</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1a</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1a</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rfc_min</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3fc0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>54</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1500</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_post_selfref_gap_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1fc000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_param_reg0@0XF8006014</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>4151a</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Parameters 0</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_param_reg1">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_param_reg1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_wr2pre</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>12</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_powerdown_to_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_faw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>15</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5400</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ras_max</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>23</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>230000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ras_min</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>13</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4c00000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_cke</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_param_reg1@0XF8006018</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f7ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>44e354d2</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Parameters 1</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_param_reg2">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg2</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_param_reg2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800601C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_write_latency</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rd2wr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_wr2rd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_xp</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tXP: Minimum time after power down exit to any operation. DRAM related.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_pad_pd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>700000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rd2pre</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:23</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f800000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rcd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>70000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_param_reg2@0XF800601C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>720238e5</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Parameters 2</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_param_reg3">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg3</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_param_reg3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006020</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ccd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rrd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_refresh_margin</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rp</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRP - Minimum time from precharge to activate of same bank. DRAM RELATED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_refresh_to_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_sdram</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: sdram device 0: non-sdram device</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mobile</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: DDR2 or DDR3 device. 1: LPDDR2 device.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_clock_stop_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:23</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_read_latency</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>28:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_mode_ddr1_ddr2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>29:29</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_pad_pd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: disable the pad power down feature 0: Enable the pad power down feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_loopback</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:31</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_param_reg3@0XF8006020</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffffffc</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>272872d0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Parameters 3</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_param_reg4">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg4</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_param_reg4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006024</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_en_2t_timing_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: DDRC will use 2T timing 0: DDRC will use 1T timing</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_prefer_write</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: Bank selector prefers writes over reads</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_max_rank_rd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3c</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr_wr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr_addr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr_data</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1fffe00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0].</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_reg_mr_wr_busy</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:25</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr_type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:26</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Indicates whether the Mode register operation is read or write 0: write 1: read</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr_rdata_valid</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_param_reg4@0XF8006024</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Parameters 4</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_init_param">Register (<A href=#mod___slcr> slcr </A>)DRAM_init_param</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_init_param</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006028</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_final_wait_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_pre_ocd_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>780</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_mrd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_init_param@0XF8006028</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2007</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Initialization Parameters</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_EMR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_EMR_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800602C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_emr2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_emr3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_EMR_reg@0XF800602C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM EMR2, EMR3 access</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_EMR_MR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_MR_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_EMR_MR_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006030</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>930</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>930</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_emr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_EMR_MR_reg@0XF8006030</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>40930</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM EMR, MR access</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_burst8_rdwr">Register (<A href=#mod___slcr> slcr </A>)DRAM_burst8_rdwr</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_burst8_rdwr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_burst_rdwr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_pre_cke_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>167</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1670</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_post_cke_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_burstchop</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>28:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Feature not supported. When 1, Controller is out in burstchop mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_burst8_rdwr@0XF8006034</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>13ff3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>11674</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Burst 8 read/write</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_disable_DQ">Register (<A href=#mod___slcr> slcr </A>)DRAM_disable_DQ</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_disable_DQ</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006038</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_force_low_pri_n</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_dq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_debug_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Not Applicable in this PHY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_level_start</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Not Applicable in this PHY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_level_start</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Not Applicable in this PHY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dq0_wait_t</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Not Applicable in this PHY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_disable_DQ@0XF8006038</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fc3</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Disable DQ</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_addr_map_bank">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_bank</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_addr_map_bank</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800603C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_bank_b0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_bank_b1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>70</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_bank_b2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>700</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_addr_map_bank@0XF800603C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>777</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Row/Column address bits</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_addr_map_col">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_col</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_addr_map_col</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006040</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b9</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f00000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b10</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b11</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f0000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_addr_map_col@0XF8006040</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>fff00000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Column address bits</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_addr_map_row">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_row</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_addr_map_row</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006044</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b2_11</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b12</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b13</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b14</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f00000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b15</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_addr_map_row@0XF8006044</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ff66666</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Select DRAM row address bits</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_ODT_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_ODT_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_ODT_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006048</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rank0_rd_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rank0_wr_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>38</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rank1_rd_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rank1_wr_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_local_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_local_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_idle_local_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rank2_rd_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rank2_wr_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rank3_rd_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rank3_wr_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>29:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>38000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_ODT_reg@0XF8006048</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3c248</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM ODT control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_cmd_timeout_rddata_cpt">Register (<A href=#mod___slcr> slcr </A>)phy_cmd_timeout_rddata_cpt</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_cmd_timeout_rddata_cpt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006050</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_cmd_to_data</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Not used in DFI PHY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_cmd_to_data</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Not used in DFI PHY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdc_we_to_re_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdc_fifo_rst_disable</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_use_fixed_re</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdc_fifo_rst_err_cnt_clr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dis_phy_ctrl_rstn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_clk_stall_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: stall clock, for DLL aging control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_num_of_dq0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_num_of_dq0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>70000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_cmd_timeout_rddata_cpt@0XF8006050</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff0f8fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>77010800</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY command time out and read data capture FIFO</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DLL_calib">Register (<A href=#mod___slcr> slcr </A>)DLL_calib</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DLL_calib</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006058</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dll_calib_to_min_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused in DFI Controller.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dll_calib_to_max_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused in DFI Controller.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_dll_calib</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DLL_calib@0XF8006058</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>101</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DLL calibration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ODT_delay_hold">Register (<A href=#mod___slcr> slcr </A>)ODT_delay_hold</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ODT_delay_hold</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800605C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rd_odt_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UNUSED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_wr_odt_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rd_odt_hold</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_wr_odt_hold</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ODT_delay_hold@0XF800605C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>5003</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ODT delay and ODT hold</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ctrl_reg1">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ctrl_reg1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006060</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_pageclose</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_lpr_num_entries</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7e</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3e</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_auto_pre_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_refresh_update_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_wc</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable Write Combine: 0: enable 1: disable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_collision_page_opt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_selfref_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ctrl_reg1@0XF8006060</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>17ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3e</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Controller 1</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ctrl_reg2">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg2</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ctrl_reg2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006064</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_go2critical_hysteresis</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1fe0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_go2critical_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ctrl_reg2@0XF8006064</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>21fe0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>20000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Controller 2</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ctrl_reg3">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg3</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ctrl_reg3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006068</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_wrlvl_ww</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>41</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>41</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rdlvl_rr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>41</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_wlmrd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>28</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>280000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ctrl_reg3@0XF8006068</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>284141</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Controller 3</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ctrl_reg4">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg4</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ctrl_reg4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800606C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dfi_t_ctrlupd_interval_min_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dfi_t_ctrlupd_interval_max_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>16</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ctrl_reg4@0XF800606C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1610</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Controller 4</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ctrl_reg5">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg5</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ctrl_reg5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006078</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_ctrl_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_dram_clk_disable</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_dram_clk_enable</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_cksre</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_cksrx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ckesr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>400000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ctrl_reg5@0XF8006078</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>466111</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Controller register 5</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ctrl_reg6">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg6</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ctrl_reg6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800607C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ckpde</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ckpdx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ckdpde</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ckdpdx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ckcsx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ctrl_reg6@0XF800607C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>32222</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Controller register 6</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_REFRESH_TIMER01">Register (<A href=#mod___slcr> slcr </A>)CHE_REFRESH_TIMER01</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_REFRESH_TIMER01</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060A0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>refresh_timer0_start_value_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>refresh_timer1_start_value_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_REFRESH_TIMER01@0XF80060A0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>8000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>CHE_REFRESH_TIMER01</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_T_ZQ">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_T_ZQ</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060A4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_auto_zq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_ddr3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_mod</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_zq_long_nop</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_zq_short_nop</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_T_ZQ@0XF80060A4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>10200802</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ZQ parameters</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_T_ZQ_Short_Interval_Reg">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ_Short_Interval_Reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_T_ZQ_Short_Interval_Reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>t_zq_short_interval_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c845</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c845</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dram_rstn_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>67</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6700000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_T_ZQ_Short_Interval_Reg@0XF80060A8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>670c845</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Misc parameters</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="deep_pwrdwn_reg">Register (<A href=#mod___slcr> slcr </A>)deep_pwrdwn_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>deep_pwrdwn_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>deeppowerdown_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>deeppowerdown_to_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1fe</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1fe</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>deep_pwrdwn_reg@0XF80060AC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1fe</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Deep powerdown (LPDDR2)</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="reg_2c">Register (<A href=#mod___slcr> slcr </A>)reg_2c</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_2c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dfi_wrlvl_max_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>fff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dfi_rdlvl_max_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>fff000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_reg_twrlvl_max_error</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_reg_trdlvl_max_error</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:25</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_wr_level_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:26</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_rd_dqs_gate_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_rd_data_eye_train</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>28:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>reg_2c@0XF80060B0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1cffffff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Training control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="reg_2d">Register (<A href=#mod___slcr> slcr </A>)reg_2d</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_2d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_2t_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_skip_ocd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_pre_bypass</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>reg_2d@0XF80060B4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Misc Debug</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="dfi_timing">Register (<A href=#mod___slcr> slcr </A>)dfi_timing</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dfi_timing</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_rddata_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_ctrlup_min</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7fe0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_ctrlup_max</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>dfi_timing@0XF80060B8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200066</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DFI timing</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_ECC_CONTROL_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_CONTROL_REG_OFFSET</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_ECC_CONTROL_REG_OFFSET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Clear_Uncorrectable_DRAM_ECC_error</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Clear_Correctable_DRAM_ECC_error</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ECC error clear</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_CORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_CORR_ECC_LOG_REG_OFFSET</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_CORR_ECC_LOG_REG_OFFSET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060C8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CORR_ECC_LOG_VALID</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ECC_CORRECTED_BIT_NUM</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fe</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ECC error correction</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_UNCORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_UNCORR_ECC_LOG_REG_OFFSET</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_UNCORR_ECC_LOG_REG_OFFSET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060DC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNCORR_ECC_LOG_VALID</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31).</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ECC unrecoverable error status</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_ECC_STATS_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_STATS_REG_OFFSET</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_ECC_STATS_REG_OFFSET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060F0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STAT_NUM_CORR_ERR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58).</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STAT_NUM_UNCORR_ERR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58).</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_ECC_STATS_REG_OFFSET@0XF80060F0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ECC error count</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ECC_scrub">Register (<A href=#mod___slcr> slcr </A>)ECC_scrub</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ECC_scrub</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060F4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_ecc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_scrub</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ECC_scrub@0XF80060F4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ECC mode/scrub</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_rcvr_enable">Register (<A href=#mod___slcr> slcr </A>)phy_rcvr_enable</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_rcvr_enable</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006114</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dif_on</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dif_off</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_rcvr_enable@0XF8006114</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Phy receiver enable register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="PHY_Config0">Register (<A href=#mod___slcr> slcr </A>)PHY_Config0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PHY_Config0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006118</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_data_slice_in_use</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_tx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_rx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_shift_dq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7fc0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_err_clr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dq_offset</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PHY_Config0@0XF8006118</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>40000001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="PHY_Config1">Register (<A href=#mod___slcr> slcr </A>)PHY_Config1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PHY_Config1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800611C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_data_slice_in_use</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_tx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_rx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_shift_dq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7fc0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_err_clr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dq_offset</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PHY_Config1@0XF800611C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>40000001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY configuration register for data slice 1.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="PHY_Config2">Register (<A href=#mod___slcr> slcr </A>)PHY_Config2</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PHY_Config2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006120</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_data_slice_in_use</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_tx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_rx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_shift_dq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7fc0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_err_clr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dq_offset</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_data_slice_in_use</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_tx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_rx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_shift_dq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7fc0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_err_clr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dq_offset</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PHY_Config2@0XF8006120</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>40000001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY configuration register for data slice 2.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="PHY_Config3">Register (<A href=#mod___slcr> slcr </A>)PHY_Config3</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PHY_Config3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006124</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_data_slice_in_use</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_tx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_rx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_shift_dq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7fc0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_err_clr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dq_offset</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PHY_Config3@0XF8006124</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>40000001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY configuration register for data slice 3.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_init_ratio0">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_init_ratio0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800612C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used by Write Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23c00</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used Gate Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_init_ratio0@0XF800612C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>23c00</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_init_ratio1">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_init_ratio1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006130</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used by Write Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8a</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used Gate Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_init_ratio1@0XF8006130</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>22800</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY init ratio register for data slice 1.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_init_ratio2">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio2</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_init_ratio2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006134</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used by Write Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22c00</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used Gate Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_init_ratio2@0XF8006134</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>22c00</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY init ratio register for data slice 2.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_init_ratio3">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio3</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_init_ratio3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006138</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used by Write Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>92</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used Gate Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_init_ratio3@0XF8006138</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>24800</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY init ratio register for data slice 3.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_rd_dqs_cfg0">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_rd_dqs_cfg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006140</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_rd_dqs_cfg0@0XF8006140</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_rd_dqs_cfg1">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_rd_dqs_cfg1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006144</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_rd_dqs_cfg1@0XF8006144</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY read DQS configuration register for data slice 1.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_rd_dqs_cfg2">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg2</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_rd_dqs_cfg2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006148</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_rd_dqs_cfg2@0XF8006148</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY read DQS configuration register for data slice 2.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_rd_dqs_cfg3">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg3</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_rd_dqs_cfg3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800614C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_rd_dqs_cfg3@0XF800614C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY read DQS configuration register for data slice 3.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_wr_dqs_cfg0">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_wr_dqs_cfg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006154</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>77</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>77</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_wr_dqs_cfg0@0XF8006154</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>77</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_wr_dqs_cfg1">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_wr_dqs_cfg1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006158</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_wr_dqs_cfg1@0XF8006158</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write DQS configuration register for data slice 1.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_wr_dqs_cfg2">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg2</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_wr_dqs_cfg2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800615C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_wr_dqs_cfg2@0XF800615C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write DQS configuration register for data slice 2.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_wr_dqs_cfg3">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg3</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_wr_dqs_cfg3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006160</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>75</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>75</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_wr_dqs_cfg3@0XF8006160</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>75</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write DQS configuration register for data slice 3.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_we_cfg0">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_we_cfg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006168</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_we_cfg0@0XF8006168</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>e4</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY FIFO write enable configuration for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_we_cfg1">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_we_cfg1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800616C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_we_cfg1@0XF800616C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY FIFO write enable configuration for data slice 1.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_we_cfg2">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg2</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_we_cfg2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006170</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_we_cfg2@0XF8006170</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>e0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY FIFO write enable configuration for data slice 2.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_we_cfg3">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg3</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_we_cfg3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006174</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e7</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_we_cfg3@0XF8006174</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>e7</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY FIFO write enable configuration for data slice 3.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="wr_data_slv0">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>wr_data_slv0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800617C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>b7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>b7</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>wr_data_slv0@0XF800617C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>b7</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write data slave ratio config for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="wr_data_slv1">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>wr_data_slv1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006180</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>bc</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>bc</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>wr_data_slv1@0XF8006180</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>bc</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write data slave ratio config for data slice 1.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="wr_data_slv2">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv2</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>wr_data_slv2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006184</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>bc</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>bc</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>wr_data_slv2@0XF8006184</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>bc</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write data slave ratio config for data slice 2.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="wr_data_slv3">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv3</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>wr_data_slv3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006188</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>b5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>b5</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>wr_data_slv3@0XF8006188</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>b5</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write data slave ratio config for data slice 3.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="reg_64">Register (<A href=#mod___slcr> slcr </A>)reg_64</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_64</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006190</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_loopback</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Loopback testing. 1: enable, 0: disable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bl2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved for future Use.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_at_spd_atpg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_enable</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_force_err</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_invert_clkout</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_all_dq_mpr_rd_resp</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_sel_logic</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_ctrl_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_ctrl_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_ctrl_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fe00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_use_rank0_delays</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>28:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_lpddr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>29:29</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: DDR2 or DDR3. 1: LPDDR2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_cmd_latency</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If set to 1, command comes to phy_ctrl through a flop.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_int_lpbk</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:31</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>reg_64@0XF8006190</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>10040080</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Training control 2</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="reg_65">Register (<A href=#mod___slcr> slcr </A>)reg_65</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_65</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006194</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_rl_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_rl_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dll_lock_diff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3c00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3c00</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_use_wr_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_use_rd_dqs_gate_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_use_rd_data_eye_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dis_calib_rst</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_ctrl_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>reg_65@0XF8006194</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1fc82</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Training control 3</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="page_mask">Register (<A href=#mod___slcr> slcr </A>)page_mask</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>page_mask</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006204</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_page_addr_mask</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>page_mask@0XF8006204</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Page mask</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_wr_port0">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_wr_port0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006208</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_rmw_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_wr_port0@0XF8006208</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>803ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_wr_port1">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_wr_port1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800620C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_rmw_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_wr_port1@0XF800620C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>803ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for write port 1.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_wr_port2">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port2</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_wr_port2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006210</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_rmw_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_wr_port2@0XF8006210</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>803ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for write port 2.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_wr_port3">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port3</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_wr_port3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006214</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_rmw_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_wr_port3@0XF8006214</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>803ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for write port 3.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_rd_port0">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_rd_port0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006218</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_set_hpr_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable reads to be generated as HPR for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_rd_port0@0XF8006218</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_rd_port1">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_rd_port1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800621C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_set_hpr_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable reads to be generated as HPR for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_rd_port1@0XF800621C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for read port 1.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_rd_port2">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port2</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_rd_port2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006220</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_set_hpr_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable reads to be generated as HPR for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_rd_port2@0XF8006220</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for read port 2.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_rd_port3">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port3</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_rd_port3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006224</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_set_hpr_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable reads to be generated as HPR for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_rd_port3@0XF8006224</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for read port 3.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="lpddr_ctrl0">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>lpddr_ctrl0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_lpddr2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: DDR2 or DDR3 in use. 1: LPDDR2 in Use.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_per_bank_refresh</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_derate_enable</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr4_margin</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UNUSED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>lpddr_ctrl0@0XF80062A8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff7</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>LPDDR2 Control 0</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="lpddr_ctrl1">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>lpddr_ctrl1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr4_read_interval</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Interval between two MR4 reads, USED to derate the timing parameters.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>lpddr_ctrl1@0XF80062AC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>LPDDR2 Control 1</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="lpddr_ctrl2">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl2</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>lpddr_ctrl2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_min_stable_clock_x1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_idle_after_reset_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>12</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>120</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Idle time after the reset command, tINIT4. Units: 32 clock cycles.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_mrw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>lpddr_ctrl2@0XF80062B0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>5125</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>LPDDR2 Control 2</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="lpddr_ctrl3">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl3</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>lpddr_ctrl3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_max_auto_init_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>a6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>a6</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dev_zqinit_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>12</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>lpddr_ctrl3@0XF80062B4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>12a6</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>LPDDR2 Control 3</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>POLL ON DCI STATUS</H1>
-<H2><a name="DDRIOB_DCI_STATUS">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_STATUS</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DCI_STATUS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B74</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DONE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI done signal</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DCI_STATUS@0XF8000B74</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>tobe</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>UNLOCK DDR</H1>
-<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_ctrl</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_soft_rstb</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_powerdown_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_data_bus_width</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_burst8_refresh</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rdwr_idle_gap</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_rd_bypass</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_act_bypass</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_auto_refresh</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ddrc_ctrl@0XF8006000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>81</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRC Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>CHECK DDR STATUS</H1>
-<H2><a name="mode_sts_reg">Register (<A href=#mod___slcr> slcr </A>)mode_sts_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>mode_sts_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006054</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_reg_operating_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>mode_sts_reg@0XF8006054</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>tobe</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-</TABLE>
-<P>
-<H2><a name="ps7_mio_init_data_2_0">ps7_mio_init_data_2_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_UNLOCK">
-SLCR_UNLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#GPIOB_CTRL">
-GPIOB_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PS IO Buffer Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_ADDR0">
-DDRIOB_ADDR0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for Address 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_ADDR1">
-DDRIOB_ADDR1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B44</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for Address 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DATA0">
-DDRIOB_DATA0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B48</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for Data 15:0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DATA1">
-DDRIOB_DATA1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B4C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for Data 31:16</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DIFF0">
-DDRIOB_DIFF0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B50</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for DQS 1:0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DIFF1">
-DDRIOB_DIFF1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B54</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for DQS 3:2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_CLOCK">
-DDRIOB_CLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B58</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for Clock Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DRIVE_SLEW_ADDR">
-DDRIOB_DRIVE_SLEW_ADDR
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B5C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Slew for Address</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DRIVE_SLEW_DATA">
-DDRIOB_DRIVE_SLEW_DATA
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Slew for Data</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DRIVE_SLEW_DIFF">
-DDRIOB_DRIVE_SLEW_DIFF
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B64</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Slew for Diff</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DRIVE_SLEW_CLOCK">
-DDRIOB_DRIVE_SLEW_CLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B68</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Slew for Clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DDR_CTRL">
-DDRIOB_DDR_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B6C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Buffer Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DCI_CTRL">
-DDRIOB_DCI_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB DCI configuration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DCI_CTRL">
-DDRIOB_DCI_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB DCI configuration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DCI_CTRL">
-DDRIOB_DCI_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB DCI configuration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_00">
-MIO_PIN_00
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000700</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 0 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_01">
-MIO_PIN_01
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000704</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 1 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_02">
-MIO_PIN_02
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000708</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 2 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_03">
-MIO_PIN_03
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800070C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 3 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_04">
-MIO_PIN_04
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000710</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 4 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_05">
-MIO_PIN_05
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000714</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 5 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_06">
-MIO_PIN_06
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000718</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 6 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_07">
-MIO_PIN_07
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800071C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 7 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_08">
-MIO_PIN_08
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000720</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 8 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_09">
-MIO_PIN_09
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000724</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 9 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_10">
-MIO_PIN_10
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000728</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 10 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_11">
-MIO_PIN_11
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800072C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 11 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_12">
-MIO_PIN_12
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000730</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 12 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_13">
-MIO_PIN_13
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000734</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 13 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_14">
-MIO_PIN_14
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000738</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 14 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_15">
-MIO_PIN_15
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800073C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 15 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_16">
-MIO_PIN_16
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000740</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 16 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_17">
-MIO_PIN_17
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000744</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 17 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_18">
-MIO_PIN_18
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000748</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 18 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_19">
-MIO_PIN_19
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800074C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 19 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_20">
-MIO_PIN_20
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000750</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 20 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_21">
-MIO_PIN_21
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000754</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 21 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_22">
-MIO_PIN_22
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000758</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 22 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_23">
-MIO_PIN_23
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800075C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 23 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_24">
-MIO_PIN_24
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000760</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 24 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_25">
-MIO_PIN_25
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000764</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 25 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_26">
-MIO_PIN_26
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000768</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 26 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_27">
-MIO_PIN_27
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800076C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 27 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_28">
-MIO_PIN_28
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000770</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 28 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_29">
-MIO_PIN_29
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000774</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 29 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_30">
-MIO_PIN_30
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000778</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 30 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_31">
-MIO_PIN_31
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800077C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 31 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_32">
-MIO_PIN_32
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000780</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 32 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_33">
-MIO_PIN_33
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000784</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 33 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_34">
-MIO_PIN_34
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000788</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 34 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_35">
-MIO_PIN_35
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800078C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 35 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_36">
-MIO_PIN_36
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000790</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 36 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_37">
-MIO_PIN_37
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000794</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 37 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_38">
-MIO_PIN_38
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000798</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 38 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_39">
-MIO_PIN_39
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800079C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 39 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_40">
-MIO_PIN_40
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 40 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_41">
-MIO_PIN_41
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 41 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_42">
-MIO_PIN_42
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 42 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_43">
-MIO_PIN_43
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 43 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_44">
-MIO_PIN_44
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 44 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_45">
-MIO_PIN_45
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 45 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_46">
-MIO_PIN_46
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 46 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_47">
-MIO_PIN_47
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007BC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 47 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_48">
-MIO_PIN_48
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 48 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_49">
-MIO_PIN_49
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 49 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_50">
-MIO_PIN_50
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 50 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_51">
-MIO_PIN_51
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007CC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 51 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_52">
-MIO_PIN_52
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007D0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 52 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_53">
-MIO_PIN_53
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007D4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Pin 53 Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SD0_WP_CD_SEL">
-SD0_WP_CD_SEL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000830</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO 0 WP CD select</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_LOCK">
-SLCR_LOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_mio_init_data_2_0">ps7_mio_init_data_2_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>SLCR SETTINGS</H1>
-<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_UNLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNLOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_UNLOCK@0XF8000008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>OCM REMAPPING</H1>
-<H2><a name="GPIOB_CTRL">Register (<A href=#mod___slcr> slcr </A>)GPIOB_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GPIOB_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VREF_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables VREF internal generator</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VREF_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables internal pullup. 0 - no pullup. 1 - pullup.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLK_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables internal pullup. 0: no pullup. 1: pullup.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRSTN_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables internal pullup. 0: no pullup. 1: pullup.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>GPIOB_CTRL@0XF8000B00</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>303</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PS IO Buffer Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DDRIOB SETTINGS</H1>
-<H2><a name="DDRIOB_ADDR0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_ADDR0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCR_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_ADDR0@0XF8000B40</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for Address 0</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_ADDR1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_ADDR1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B44</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCR_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_ADDR1@0XF8000B44</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for Address 1</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DATA0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B48</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCR_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DATA0@0XF8000B48</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>672</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for Data 15:0</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DATA1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B4C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCR_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DATA1@0XF8000B4C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>672</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for Data 31:16</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DIFF0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B50</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCR_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DIFF0@0XF8000B50</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>674</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for DQS 1:0</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DIFF1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B54</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCR_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DIFF1@0XF8000B54</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>674</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for DQS 3:2</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_CLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_CLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B58</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCR_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0: no pullup 1: pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_CLOCK@0XF8000B58</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for Clock Output</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DRIVE_SLEW_ADDR">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_ADDR</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DRIVE_SLEW_ADDR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B5C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRIVE_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIO drive strength for the P devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRIVE_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIO drive strength for the N devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLEW_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIO slew rate for the P devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLEW_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>180000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIO slew rate for the N devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GTL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Test Control 000: Normal Operation 001 to 111: Test Mode</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RTERM</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Program the rterm</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>18c61c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Slew for Address</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DRIVE_SLEW_DATA">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DATA</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DRIVE_SLEW_DATA</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRIVE_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIO drive strength for the P devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRIVE_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIO drive strength for the N devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLEW_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIO slew rate for the P devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLEW_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIO slew rate for the N devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GTL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Test Control 000: Normal Operation 001 to 111: Test Mode</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RTERM</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Program the rterm</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DRIVE_SLEW_DATA@0XF8000B60</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>f9861c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Slew for Data</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DRIVE_SLEW_DIFF">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DIFF</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DRIVE_SLEW_DIFF</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B64</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRIVE_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIO drive strength for the P devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRIVE_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIO drive strength for the N devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLEW_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIO slew rate for the P devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLEW_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIO slew rate for the N devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GTL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Test Control 000: Normal Operation 001 to 111: Test Mode</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RTERM</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Program the rterm</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>f9861c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Slew for Diff</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DRIVE_SLEW_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_CLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DRIVE_SLEW_CLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B68</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRIVE_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIO drive strength for the P devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRIVE_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIO drive strength for the N devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLEW_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIO slew rate for the P devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLEW_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIO slew rate for the N devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GTL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Test Control 000: Normal Operation 001 to 111: Test Mode</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RTERM</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Program the rterm</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>f9861c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Slew for Clock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DDR_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DDR_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DDR_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B6C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VREF_INT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables VREF internal generator</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VREF_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1e</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VREF_EXT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VREF_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>REFIO_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>REFIO_TEST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>REFIO_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRST_B_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables pull-up resistors 0: no pull-up 1: enable pull-up</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CKE_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables pull-up resistors 0: no pull-up 1: enable pull-up</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DDR_CTRL@0XF8000B6C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>260</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Buffer Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ASSERT RESET</H1>
-<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DCI_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>At least toggle once to initialise flops in DCI system</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VRN_OUT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>VRN output value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>21</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>21</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB DCI configuration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DEASSERT RESET</H1>
-<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DCI_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>At least toggle once to initialise flops in DCI system</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VRN_OUT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>VRN output value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>21</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB DCI configuration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DCI_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>At least toggle once to initialise flops in DCI system</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1 if any iob's use a terminate type, or if dci test block used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VRP_TRI</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>VRP tristate value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VRN_TRI</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>VRN tristate value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VRP_OUT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>VRP output value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VRN_OUT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>VRN output value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>NREF_OPT1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>NREF_OPT2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>700</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>NREF_OPT4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PREF_OPT1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PREF_OPT2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UPDATE_CONTROL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INIT_COMPLETE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>test Internal to IO bank</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TST_CLK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Emulate DCI clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TST_HLN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:23</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Emulate comparator output (VRN)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TST_HLP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Emulate comparator output (VRP)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TST_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:25</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Emulate Reset</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INT_DCI_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:26</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Need explanation here</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>823</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB DCI configuration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MIO PROGRAMMING</H1>
-<H2><a name="MIO_PIN_00">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_00</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_00</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000700</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high. 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables pull-up on IO Buffer pin 0: disable 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_00@0XF8000700</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 0 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_01">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_01</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_01</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000704</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_01@0XF8000704</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 1 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_02">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_02</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_02</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000708</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_02@0XF8000708</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 2 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_03">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_03</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_03</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800070C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_03@0XF800070C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 3 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_04">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_04</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_04</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000710</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_04@0XF8000710</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 4 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_05">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_05</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_05</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000714</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_05@0XF8000714</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 5 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_06">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_06</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_06</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000718</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_06@0XF8000718</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 6 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_07">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_07</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_07</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800071C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_07@0XF800071C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 7 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_08">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_08</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_08</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000720</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_08@0XF8000720</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 8 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_09">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_09</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_09</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000724</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_09@0XF8000724</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 9 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_10">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_10</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_10</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000728</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_10@0XF8000728</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1640</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 10 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_11">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_11</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_11</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800072C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_11@0XF800072C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1640</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 11 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_12">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_12</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_12</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000730</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_12@0XF8000730</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1640</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 12 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_13">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_13</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_13</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000734</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_13@0XF8000734</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1640</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 13 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_14">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_14</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_14</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000738</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_14@0XF8000738</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 14 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_15">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_15</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_15</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800073C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_15@0XF800073C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 15 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_16">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_16</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_16</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000740</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_16@0XF8000740</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 16 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_17">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_17</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_17</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000744</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_17@0XF8000744</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 17 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_18">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_18</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_18</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000748</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_18@0XF8000748</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 18 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_19">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_19</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_19</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800074C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_19@0XF800074C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 19 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_20">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_20</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_20</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000750</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_20@0XF8000750</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 20 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_21">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_21</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_21</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000754</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_21@0XF8000754</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 21 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_22">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_22</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_22</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000758</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_22@0XF8000758</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 22 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_23">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_23</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_23</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800075C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_23@0XF800075C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 23 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_24">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_24</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_24</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000760</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_24@0XF8000760</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 24 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_25">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_25</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_25</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000764</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_25@0XF8000764</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 25 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_26">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_26</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_26</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000768</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_26@0XF8000768</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 26 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_27">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_27</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_27</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800076C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_27@0XF800076C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 27 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_28">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_28</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_28</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000770</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_28@0XF8000770</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 28 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_29">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_29</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_29</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000774</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_29@0XF8000774</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>305</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 29 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_30">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_30</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_30</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000778</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_30@0XF8000778</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 30 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_31">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_31</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_31</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800077C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_31@0XF800077C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>305</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 31 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_32">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_32</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000780</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_32@0XF8000780</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 32 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_33">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_33</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_33</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000784</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_33@0XF8000784</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 33 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_34">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_34</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_34</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000788</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_34@0XF8000788</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 34 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_35">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_35</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_35</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800078C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_35@0XF800078C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 35 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_36">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_36</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_36</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000790</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_36@0XF8000790</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>305</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 36 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_37">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_37</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_37</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000794</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_37@0XF8000794</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 37 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_38">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_38</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_38</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000798</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_38@0XF8000798</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 38 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_39">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_39</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_39</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800079C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_39@0XF800079C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 39 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_40">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_40</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_40@0XF80007A0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 40 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_41">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_41</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_41</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_41@0XF80007A4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 41 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_42">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_42</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_42</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_42@0XF80007A8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 42 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_43">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_43</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_43</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_43@0XF80007AC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 43 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_44">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_44</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_44</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_44@0XF80007B0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 44 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_45">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_45</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_45</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_45@0XF80007B4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 45 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_46">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_46</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_46</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_46@0XF80007B8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 46 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_47">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_47</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_47</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007BC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_47@0XF80007BC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f01</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>201</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 47 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_48">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_48</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_48</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_48@0XF80007C0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2e0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 48 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_49">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_49</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_49</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_49@0XF80007C4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2e1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 49 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_50">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_50</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_50</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_50@0XF80007C8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 50 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_51">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_51</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_51</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007CC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_51@0XF80007CC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 51 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_52">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_52</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_52</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007D0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_52@0XF80007D0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 52 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_53">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_53</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_53</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007D4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[TRI_ENABLE]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0: Level 1 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0: Level 2 Mux 1: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[Speed]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[IO_Type]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[PULL_UP]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operates the same as MIO_PIN_00[DisableRcvr]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_53@0XF80007D4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Pin 53 Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="SD0_WP_CD_SEL">Register (<A href=#mod___slcr> slcr </A>)SD0_WP_CD_SEL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SD0_WP_CD_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000830</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SDIO0_WP_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>37</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>37</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SDIO0_CD_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2f0000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SD0_WP_CD_SEL@0XF8000830</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f003f</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2f0037</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SDIO 0 WP CD select</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>LOCK IT BACK</H1>
-<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_LOCK@0XF8000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-</TABLE>
-<P>
-<H2><a name="ps7_peripherals_init_data_2_0">ps7_peripherals_init_data_2_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_UNLOCK">
-SLCR_UNLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DATA0">
-DDRIOB_DATA0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B48</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for Data 15:0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DATA1">
-DDRIOB_DATA1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B4C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for Data 31:16</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DIFF0">
-DDRIOB_DIFF0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B50</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for DQS 1:0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DIFF1">
-DDRIOB_DIFF1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B54</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR IOB Config for DQS 3:2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_LOCK">
-SLCR_LOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Baud_rate_divider_reg0">
-Baud_rate_divider_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>baud rate divider register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Baud_rate_gen_reg0">
-Baud_rate_gen_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud rate divider register.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Control_reg0">
-Control_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART Control register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#mode_reg0">
-mode_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART Mode register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Baud_rate_divider_reg0">
-Baud_rate_divider_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>baud rate divider register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Baud_rate_gen_reg0">
-Baud_rate_gen_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud rate divider register.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Control_reg0">
-Control_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART Control register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#mode_reg0">
-mode_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART Mode register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Config_reg">
-Config_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000D000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SPI configuration register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CTRL">
-CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8007000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DIRM_1">
-DIRM_1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A244</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Direction mode (GPIO Bank1, MIO)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MASK_DATA_1_LSW">
-MASK_DATA_1_LSW
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#OEN_1">
-OEN_1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A248</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Output enable (GPIO Bank1, MIO)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MASK_DATA_1_LSW">
-MASK_DATA_1_LSW
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MASK_DATA_1_LSW">
-MASK_DATA_1_LSW
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_peripherals_init_data_2_0">ps7_peripherals_init_data_2_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>SLCR SETTINGS</H1>
-<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_UNLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNLOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_UNLOCK@0XF8000008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DDR TERM/IBUF_DISABLE_MODE SETTINGS</H1>
-<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DATA0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B48</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DATA0@0XF8000B48</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for Data 15:0</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DATA1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B4C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DATA1@0XF8000B4C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for Data 31:16</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DIFF0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B50</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DIFF0@0XF8000B50</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for DQS 1:0</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DIFF1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B54</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DIFF1@0XF8000B54</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR IOB Config for DQS 3:2</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>LOCK IT BACK</H1>
-<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_LOCK@0XF8000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>SRAM/NOR SET OPMODE</H1>
-<H1>UART REGISTERS</H1>
-<H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Baud_rate_divider_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>BDIV</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Baud_rate_divider_reg0@0XE0001034</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>baud rate divider register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Baud_rate_gen_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CD</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Baud_rate_gen_reg0@0XE0001018</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Baud rate divider register.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Control_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STPBRK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Stop transmitter break: 0: start break transmission, 1: stop break transmission.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STTBRK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RSTTO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXDIS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Transmit disable: 0: enable transmitter, 0: disable transmitter</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXEN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXDIS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Receive disable: 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXEN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXRES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXRES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Control_reg0@0XE0001000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>17</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>UART Control register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>mode_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IRMODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UCLKEN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHMODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>300</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>NBSTOP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PAR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>38</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>mode_reg0@0XE0001004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>UART Mode register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Baud_rate_divider_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>BDIV</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Baud_rate_divider_reg0@0XE0000034</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>baud rate divider register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Baud_rate_gen_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CD</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Baud_rate_gen_reg0@0XE0000018</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Baud rate divider register.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Control_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STPBRK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Stop transmitter break: 0: start break transmission, 1: stop break transmission.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STTBRK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RSTTO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXDIS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Transmit disable: 0: enable transmitter, 0: disable transmitter</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXEN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXDIS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Receive disable: 0: disable, 1: enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXEN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXRES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXRES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Control_reg0@0XE0000000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>17</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>UART Control register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>mode_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IRMODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UCLKEN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHMODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>300</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>NBSTOP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PAR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>38</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>mode_reg0@0XE0000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>UART Mode register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>QSPI REGISTERS</H1>
-<H2><a name="Config_reg">Register (<A href=#mod___slcr> slcr </A>)Config_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Config_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000D000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Holdb_dr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Config_reg@0XE000D000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SPI configuration register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>PL POWER ON RESET REGISTERS</H1>
-<H2><a name="CTRL">Register (<A href=#mod___slcr> slcr </A>)CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8007000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PCFG_POR_CNT_4K</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>29:29</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CTRL@0XF8007000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>20000000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>SMC TIMING CALCULATION REGISTER UPDATE</H1>
-<H1>NAND SET CYCLE</H1>
-<H1>OPMODE</H1>
-<H1>DIRECT COMMAND</H1>
-<H1>SRAM/NOR CS0 SET CYCLE</H1>
-<H1>DIRECT COMMAND</H1>
-<H1>NOR CS0 BASE ADDRESS</H1>
-<H1>SRAM/NOR CS1 SET CYCLE</H1>
-<H1>DIRECT COMMAND</H1>
-<H1>NOR CS1 BASE ADDRESS</H1>
-<H1>USB RESET</H1>
-<H1>USB0 RESET</H1>
-<H1>DIR MODE BANK 0</H1>
-<H1>DIR MODE BANK 1</H1>
-<H2><a name="DIRM_1">Register (<A href=#mod___slcr> slcr </A>)DIRM_1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIRM_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A244</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIRECTION_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operation is the same as DIRM_0[DIRECTION_0]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DIRM_1@0XE000A244</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Direction mode (GPIO Bank1, MIO)</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>bfff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>bfff0000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MASK_DATA_1_LSW@0XE000A008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>bfff4000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE BANK 0</H1>
-<H1>OUTPUT ENABLE BANK 1</H1>
-<H2><a name="OEN_1">Register (<A href=#mod___slcr> slcr </A>)OEN_1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OEN_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A248</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OP_ENABLE_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operation is the same as OEN_0[OP_ENABLE_0]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>OEN_1@0XE000A248</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Output enable (GPIO Bank1, MIO)</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>bfff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>bfff0000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MASK_DATA_1_LSW@0XE000A008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>bfff0000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>bfff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>bfff0000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MASK_DATA_1_LSW@0XE000A008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>bfff4000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>USB1 RESET</H1>
-<H1>DIR MODE BANK 0</H1>
-<H1>DIR MODE BANK 1</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE BANK 0</H1>
-<H1>OUTPUT ENABLE BANK 1</H1>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>ENET RESET</H1>
-<H1>ENET0 RESET</H1>
-<H1>DIR MODE BANK 0</H1>
-<H1>DIR MODE BANK 1</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE BANK 0</H1>
-<H1>OUTPUT ENABLE BANK 1</H1>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>ENET1 RESET</H1>
-<H1>DIR MODE BANK 0</H1>
-<H1>DIR MODE BANK 1</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE BANK 0</H1>
-<H1>OUTPUT ENABLE BANK 1</H1>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>I2C RESET</H1>
-<H1>I2C0 RESET</H1>
-<H1>DIR MODE GPIO BANK0</H1>
-<H1>DIR MODE GPIO BANK1</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE</H1>
-<H1>OUTPUT ENABLE</H1>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>I2C1 RESET</H1>
-<H1>DIR MODE GPIO BANK0</H1>
-<H1>DIR MODE GPIO BANK1</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE</H1>
-<H1>OUTPUT ENABLE</H1>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>NOR CHIP SELECT</H1>
-<H1>DIR MODE BANK 0</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>OUTPUT ENABLE BANK 0</H1>
-</TABLE>
-<P>
-<H2><a name="ps7_post_config_2_0">ps7_post_config_2_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_UNLOCK">
-SLCR_UNLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LVL_SHFTR_EN">
-LVL_SHFTR_EN
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000900</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level Shifters Enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#FPGA_RST_CTRL">
-FPGA_RST_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000240</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA Software Reset Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_LOCK">
-SLCR_LOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_post_config_2_0">ps7_post_config_2_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>SLCR SETTINGS</H1>
-<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_UNLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNLOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_UNLOCK@0XF8000008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ENABLING LEVEL SHIFTER</H1>
-<H2><a name="LVL_SHFTR_EN">Register (<A href=#mod___slcr> slcr </A>)LVL_SHFTR_EN</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LVL_SHFTR_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000900</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>USER_INP_ICT_EN_0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0].</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>USER_INP_ICT_EN_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0].</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LVL_SHFTR_EN@0XF8000900</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>f</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Level Shifters Enable</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>FPGA RESETS TO 0</H1>
-<H2><a name="FPGA_RST_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA_RST_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_RST_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000240</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:25</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fe000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Writes are ignored, read data is zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_ACP_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_AXDS3_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:23</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_AXDS2_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_AXDS1_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_AXDS0_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Writes are ignored, read data is zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FSSW1_FPGA_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FSSW0_FPGA_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Writes are ignored, read data is zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_FMSW1_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_FMSW0_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_DMA3_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_DMA2_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_DMA1_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_DMA0_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Writes are ignored, read data is zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA3_OUT_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA2_OUT_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA1_OUT_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA0_OUT_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>FPGA_RST_CTRL@0XF8000240</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>FPGA Software Reset Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>AFI REGISTERS</H1>
-<H1>AFI0 REGISTERS</H1>
-<H1>AFI1 REGISTERS</H1>
-<H1>AFI2 REGISTERS</H1>
-<H1>AFI3 REGISTERS</H1>
-<H1>LOCK IT BACK</H1>
-<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_LOCK@0XF8000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-</TABLE>
-<P>
-<H2><a name="ps7_debug_2_0">ps7_debug_2_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LAR">
-LAR
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8898FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LAR">
-LAR
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8899FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LAR">
-LAR
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8809FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_debug_2_0">ps7_debug_2_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>CROSS TRIGGER CONFIGURATIONS</H1>
-<H1>UNLOCKING CTI REGISTERS</H1>
-<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LAR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8898FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LAR@0XF8898FB0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LAR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8899FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LAR@0XF8899FB0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LAR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8809FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LAR@0XF8809FB0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ENABLING CTI MODULES AND CHANNELS</H1>
-<H1>MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS</H1>
-</TABLE>
-<P>
-</body>
-</head>
-</body>
-</html>
-<H2><a name="ps7_pll_init_data_1_0">ps7_pll_init_data_1_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_UNLOCK">
-SLCR_UNLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CFG">
-ARM_PLL_CFG
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000110</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Configuration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CTRL">
-ARM_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CTRL">
-ARM_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CTRL">
-ARM_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CTRL">
-ARM_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_PLL_CTRL">
-ARM_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ARM_CLK_CTRL">
-ARM_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000120</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CORTEX A9 Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CFG">
-DDR_PLL_CFG
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000114</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Configuration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CTRL">
-DDR_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CTRL">
-DDR_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CTRL">
-DDR_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CTRL">
-DDR_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_PLL_CTRL">
-DDR_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDR_CLK_CTRL">
-DDR_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000124</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CFG">
-IO_PLL_CFG
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000118</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Configuration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CTRL">
-IO_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CTRL">
-IO_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CTRL">
-IO_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CTRL">
-IO_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#IO_PLL_CTRL">
-IO_PLL_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_LOCK">
-SLCR_LOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_pll_init_data_1_0">ps7_pll_init_data_1_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>SLCR SETTINGS</H1>
-<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_UNLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNLOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_UNLOCK@0XF8000008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>PLL SLCR REGISTERS</H1>
-<H1>ARM PLL INIT</H1>
-<H2><a name="ARM_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CFG</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CFG</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000110</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_CP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_CNT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>177</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>177000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CFG@0XF8000110</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffff0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1772c0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Configuration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>UPDATE FB_DIV</H1>
-<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_FDIV</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1a</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1a000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CTRL@0XF8000100</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1a000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>BY PASS PLL</H1>
-<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CTRL@0XF8000100</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ASSERT RESET</H1>
-<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CTRL@0XF8000100</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DEASSERT RESET</H1>
-<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CTRL@0XF8000100</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>CHECK PLL STATUS</H1>
-<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_STATUS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800010C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PLL_STATUS@0XF800010C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>tobe</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>REMOVE PLL BY PASS</H1>
-<H2><a name="ARM_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_PLL_CTRL@0XF8000100</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ARM PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ARM_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)ARM_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ARM_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000120</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CPU_6OR4XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CPU_3OR2XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:25</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CPU_2XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:26</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CPU_PERI_CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>28:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ARM_CLK_CTRL@0XF8000120</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1f003f30</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1f000200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>CORTEX A9 Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DDR PLL INIT</H1>
-<H2><a name="DDR_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CFG</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CFG</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000114</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_CP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_CNT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1db</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1db000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CFG@0XF8000114</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffff0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1db2c0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Configuration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>UPDATE FB_DIV</H1>
-<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_FDIV</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>15</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CTRL@0XF8000104</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>15000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>BY PASS PLL</H1>
-<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CTRL@0XF8000104</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ASSERT RESET</H1>
-<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CTRL@0XF8000104</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DEASSERT RESET</H1>
-<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CTRL@0XF8000104</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>CHECK PLL STATUS</H1>
-<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_STATUS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800010C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PLL_STATUS@0XF800010C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>tobe</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>REMOVE PLL BY PASS</H1>
-<H2><a name="DDR_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000104</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_PLL_CTRL@0XF8000104</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDR_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDR_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000124</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_3XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_2XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_3XCLK_DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Divisor value for the ddr_3xclk</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDR_2XCLK_DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:26</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fc000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDR_CLK_CTRL@0XF8000124</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff00003</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>c200003</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDR Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>IO PLL INIT</H1>
-<H2><a name="IO_PLL_CFG">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CFG</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CFG</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000118</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_CP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_CNT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1f4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CFG@0XF8000118</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffff0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1f42c0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Configuration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>UPDATE FB_DIV</H1>
-<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_FDIV</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>14</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CTRL@0XF8000108</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7f000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>14000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>BY PASS PLL</H1>
-<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CTRL@0XF8000108</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ASSERT RESET</H1>
-<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CTRL@0XF8000108</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DEASSERT RESET</H1>
-<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CTRL@0XF8000108</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>CHECK PLL STATUS</H1>
-<H2><a name="PLL_STATUS">Register (<A href=#mod___slcr> slcr </A>)PLL_STATUS</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_STATUS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800010C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PLL_STATUS@0XF800010C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>tobe</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>REMOVE PLL BY PASS</H1>
-<H2><a name="IO_PLL_CTRL">Register (<A href=#mod___slcr> slcr </A>)IO_PLL_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_PLL_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000108</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PLL_BYPASS_FORCE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>IO_PLL_CTRL@0XF8000108</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>IO PLL Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>LOCK IT BACK</H1>
-<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_LOCK@0XF8000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-</TABLE>
-<P>
-<H2><a name="ps7_clock_init_data_1_0">ps7_clock_init_data_1_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_UNLOCK">
-SLCR_UNLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DCI_CLK_CTRL">
-DCI_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000128</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI clock control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#GEM0_RCLK_CTRL">
-GEM0_RCLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000138</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Gigabit Ethernet MAC 0 RX Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#GEM0_CLK_CTRL">
-GEM0_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000140</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Gigabit Ethernet MAC 0 Ref Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LQSPI_CLK_CTRL">
-LQSPI_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800014C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Linear Quad-SPI Reference Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SDIO_CLK_CTRL">
-SDIO_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000150</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO Reference Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#UART_CLK_CTRL">
-UART_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000154</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART Reference Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#PCAP_CLK_CTRL">
-PCAP_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000168</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PCAP 2X Clock Contol</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#FPGA0_CLK_CTRL">
-FPGA0_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000170</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA 0 Output Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CLK_621_TRUE">
-CLK_621_TRUE
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80001C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>6:2:1 ratio clock, if set</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#APER_CLK_CTRL">
-APER_CLK_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800012C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AMBA Peripheral Clock Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_LOCK">
-SLCR_LOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_clock_init_data_1_0">ps7_clock_init_data_1_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>SLCR SETTINGS</H1>
-<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_UNLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNLOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_UNLOCK@0XF8000008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>CLOCK CONTROL SLCR REGISTERS</H1>
-<H2><a name="DCI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)DCI_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000128</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>34</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3400</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DCI_CLK_CTRL@0XF8000128</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f03f01</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>203401</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DCI clock control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="GEM0_RCLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_RCLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GEM0_RCLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000138</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>GEM0_RCLK_CTRL@0XF8000138</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>11</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Gigabit Ethernet MAC 0 RX Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="GEM0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)GEM0_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GEM0_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000140</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>GEM0_CLK_CTRL@0XF8000140</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f03f71</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>100801</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Gigabit Ethernet MAC 0 Ref Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="LQSPI_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)LQSPI_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LQSPI_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800014C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>500</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LQSPI_CLK_CTRL@0XF800014C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f31</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>501</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Linear Quad-SPI Reference Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="SDIO_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)SDIO_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SDIO_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000150</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>14</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1400</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SDIO_CLK_CTRL@0XF8000150</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f33</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1401</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SDIO Reference Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="UART_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)UART_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UART_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000154</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>a</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>a00</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>UART_CLK_CTRL@0XF8000154</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f33</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>a03</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>UART Reference Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>TRACE CLOCK</H1>
-<H2><a name="PCAP_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)PCAP_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PCAP_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000168</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clock active 0 - Clock is disabled 1 - Clock is enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>500</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PCAP_CLK_CTRL@0XF8000168</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f31</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>501</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PCAP 2X Clock Contol</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="FPGA0_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA0_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA0_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000170</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRCSEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>500</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIVISOR1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>FPGA0_CLK_CTRL@0XF8000170</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f03f30</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200500</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>FPGA 0 Output Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CLK_621_TRUE">Register (<A href=#mod___slcr> slcr </A>)CLK_621_TRUE</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLK_621_TRUE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80001C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLK_621_TRUE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CLK_621_TRUE@0XF80001C4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>6:2:1 ratio clock, if set</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="APER_CLK_CTRL">Register (<A href=#mod___slcr> slcr </A>)APER_CLK_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>APER_CLK_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800012C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DMA_CPU_2XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>USB0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>USB1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GEM0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GEM1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SDI0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SDI1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SPI0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SPI1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CAN0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CAN1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>I2C0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>I2C1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UART0_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UART1_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GPIO_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>400000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LQSPI_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:23</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SMC_CPU_1XCLKACT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>APER_CLK_CTRL@0XF800012C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ffcccd</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1fc044d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AMBA Peripheral Clock Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>THIS SHOULD BE BLANK</H1>
-<H1>LOCK IT BACK</H1>
-<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_LOCK@0XF8000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-</TABLE>
-<P>
-<H2><a name="ps7_ddr_init_data_1_0">ps7_ddr_init_data_1_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ddrc_ctrl">
-ddrc_ctrl
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRC Control Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Two_rank_cfg">
-Two_rank_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Two rank configuration register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#HPR_reg">
-HPR_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>HPR Queue control register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LPR_reg">
-LPR_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800600C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>LPR Queue control register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#WR_reg">
-WR_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006010</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>WR Queue control register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_param_reg0">
-DRAM_param_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006014</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Parameters register 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_param_reg1">
-DRAM_param_reg1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Parameters register 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_param_reg2">
-DRAM_param_reg2
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800601C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Parameters register 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_param_reg3">
-DRAM_param_reg3
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006020</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Parameters register 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_param_reg4">
-DRAM_param_reg4
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006024</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Parameters register 4</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_init_param">
-DRAM_init_param
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006028</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM initialization parameters register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_EMR_reg">
-DRAM_EMR_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800602C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM EMR2, EMR3 access register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_EMR_MR_reg">
-DRAM_EMR_MR_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006030</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM EMR, MR access register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_burst8_rdwr">
-DRAM_burst8_rdwr
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM burst 8 read/write register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_disable_DQ">
-DRAM_disable_DQ
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006038</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM Disable DQ register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_addr_map_bank">
-DRAM_addr_map_bank
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800603C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the address bits used as DRAM bank address bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_addr_map_col">
-DRAM_addr_map_col
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006040</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the address bits used as DRAM column address bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_addr_map_row">
-DRAM_addr_map_row
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006044</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the address bits used as DRAM row address bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DRAM_ODT_reg">
-DRAM_ODT_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006048</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM ODT register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_cmd_timeout_rddata_cpt">
-phy_cmd_timeout_rddata_cpt
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006050</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY command time out and read data capture FIFO register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DLL_calib">
-DLL_calib
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006058</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DLL calibration register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ODT_delay_hold">
-ODT_delay_hold
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800605C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ODT delay and ODT hold register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ctrl_reg1">
-ctrl_reg1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006060</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller register 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ctrl_reg2">
-ctrl_reg2
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006064</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller register 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ctrl_reg3">
-ctrl_reg3
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006068</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller register 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ctrl_reg4">
-ctrl_reg4
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800606C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller register 4</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_REFRESH_TIMER01">
-CHE_REFRESH_TIMER01
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060A0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>CHE_REFRESH_TIMER01</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_T_ZQ">
-CHE_T_ZQ
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060A4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ZQ parameters register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_T_ZQ_Short_Interval_Reg">
-CHE_T_ZQ_Short_Interval_Reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Misc parameters register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#deep_pwrdwn_reg">
-deep_pwrdwn_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Deep powerdown register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#reg_2c">
-reg_2c
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Training control register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#reg_2d">
-reg_2d
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Misc Debug register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#dfi_timing">
-dfi_timing
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DFI timing register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_ECC_CONTROL_REG_OFFSET">
-CHE_ECC_CONTROL_REG_OFFSET
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ECC error clear register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_CORR_ECC_LOG_REG_OFFSET">
-CHE_CORR_ECC_LOG_REG_OFFSET
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060C8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ECC error correction register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_UNCORR_ECC_LOG_REG_OFFSET">
-CHE_UNCORR_ECC_LOG_REG_OFFSET
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060DC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ECC unrecoverable error status register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CHE_ECC_STATS_REG_OFFSET">
-CHE_ECC_STATS_REG_OFFSET
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060F0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ECC error count register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ECC_scrub">
-ECC_scrub
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060F4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ECC mode/scrub register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_rcvr_enable">
-phy_rcvr_enable
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006114</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Phy receiver enable register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#PHY_Config">
-PHY_Config
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006118</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#PHY_Config">
-PHY_Config
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800611C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#PHY_Config">
-PHY_Config
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006120</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#PHY_Config">
-PHY_Config
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006124</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_init_ratio">
-phy_init_ratio
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800612C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_init_ratio">
-phy_init_ratio
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006130</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_init_ratio">
-phy_init_ratio
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006134</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_init_ratio">
-phy_init_ratio
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006138</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_rd_dqs_cfg">
-phy_rd_dqs_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006140</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_rd_dqs_cfg">
-phy_rd_dqs_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006144</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_rd_dqs_cfg">
-phy_rd_dqs_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006148</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_rd_dqs_cfg">
-phy_rd_dqs_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800614C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_wr_dqs_cfg">
-phy_wr_dqs_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006154</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_wr_dqs_cfg">
-phy_wr_dqs_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006158</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_wr_dqs_cfg">
-phy_wr_dqs_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800615C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_wr_dqs_cfg">
-phy_wr_dqs_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006160</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_we_cfg">
-phy_we_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006168</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY fifo write enable configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_we_cfg">
-phy_we_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800616C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY fifo write enable configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_we_cfg">
-phy_we_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006170</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY fifo write enable configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#phy_we_cfg">
-phy_we_cfg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006174</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY fifo write enable configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#wr_data_slv">
-wr_data_slv
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800617C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write data slave ratio configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#wr_data_slv">
-wr_data_slv
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006180</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write data slave ratio configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#wr_data_slv">
-wr_data_slv
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006184</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write data slave ratio configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#wr_data_slv">
-wr_data_slv
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006188</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>PHY write data slave ratio configuration register for data slice 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#reg_64">
-reg_64
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006190</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Training control register (2)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#reg_65">
-reg_65
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006194</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Training control register (3)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#page_mask">
-page_mask
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006204</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Page mask register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_wr_port">
-axi_priority_wr_port
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006208</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_wr_port">
-axi_priority_wr_port
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800620C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_wr_port">
-axi_priority_wr_port
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006210</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_wr_port">
-axi_priority_wr_port
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006214</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_rd_port">
-axi_priority_rd_port
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006218</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_rd_port">
-axi_priority_rd_port
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800621C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_rd_port">
-axi_priority_rd_port
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006220</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#axi_priority_rd_port">
-axi_priority_rd_port
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006224</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#lpddr_ctrl0">
-lpddr_ctrl0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>LPDDR2 Control 0 Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#lpddr_ctrl1">
-lpddr_ctrl1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>LPDDR2 Control 1 Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#lpddr_ctrl2">
-lpddr_ctrl2
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>LPDDR2 Control 2 Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#lpddr_ctrl3">
-lpddr_ctrl3
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>LPDDR2 Control 3 Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#ddrc_ctrl">
-ddrc_ctrl
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRC Control Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_ddr_init_data_1_0">ps7_ddr_init_data_1_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>DDR INITIALIZATION</H1>
-<H1>LOCK DDR</H1>
-<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_ctrl</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_soft_rstb</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_powerdown_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_data_bus_width</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_burst8_refresh</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rdwr_idle_gap</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_rd_bypass</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_act_bypass</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_auto_refresh</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ddrc_ctrl@0XF8006000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRC Control Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Two_rank_cfg">Register (<A href=#mod___slcr> slcr </A>)Two_rank_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Two_rank_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rfc_nom_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_active_ranks</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_cs_bit0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_wr_odt_block</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>180000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_diff_rank_rd_2cycle_gap</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_cs_bit1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_open_bank</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_4bank_ram</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>28:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Two_rank_cfg@0XF8006004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>8107f</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Two rank configuration register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="HPR_reg">Register (<A href=#mod___slcr> slcr </A>)HPR_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>HPR_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_hpr_min_non_critical_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_hpr_max_starve_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_hpr_xact_run_length</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3c00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3c00000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>HPR_reg@0XF8006008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3c0780f</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>HPR Queue control register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="LPR_reg">Register (<A href=#mod___slcr> slcr </A>)LPR_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LPR_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800600C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_lpr_min_non_critical_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_lpr_max_starve_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_lpr_xact_run_length</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3c00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LPR_reg@0XF800600C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2001001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>LPR Queue control register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="WR_reg">Register (<A href=#mod___slcr> slcr </A>)WR_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>WR_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006010</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_w_min_non_critical_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of clock cycles that the WR queue is guaranteed to be non-critical.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_w_xact_run_length</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_w_max_starve_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>WR_reg@0XF8006010</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>14001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>WR Queue control register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_param_reg0">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_param_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006014</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rc</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1a</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1a</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rfc_min</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3fc0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>54</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1500</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_post_selfref_gap_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1fc000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_param_reg0@0XF8006014</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>4151a</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Parameters register 0</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_param_reg1">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_param_reg1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_wr2pre</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>12</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_powerdown_to_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_faw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>15</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5400</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ras_max</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>23</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>230000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ras_min</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>13</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4c00000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_cke</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_param_reg1@0XF8006018</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f7ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>44e354d2</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Parameters register 1</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_param_reg2">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg2</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_param_reg2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800601C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_write_latency</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rd2wr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_wr2rd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_xp</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tXP: Minimum time after power down exit to any operation. DRAM RELATED.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_pad_pd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>700000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rd2pre</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:23</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f800000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rcd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>70000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_param_reg2@0XF800601C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>720238e5</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Parameters register 2</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_param_reg3">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg3</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_param_reg3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006020</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_ccd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rrd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_refresh_margin</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_rp</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tRP - Minimum time from precharge to activate of same bank. DRAM RELATED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_refresh_to_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_sdram</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1 = sdram device 0 = non-sdram device</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mobile</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_clock_stop_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:23</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_read_latency</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>28:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_mode_ddr1_ddr2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>29:29</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_pad_pd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1 = disable the pad power down feature 0 = Enable the pad power down feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_loopback</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:31</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_param_reg3@0XF8006020</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffffffc</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>272872d0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Parameters register 3</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_param_reg4">Register (<A href=#mod___slcr> slcr </A>)DRAM_param_reg4</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_param_reg4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006024</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_en_2t_timing_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1 = DDRC will use 2T timing 0 = DDRC will use 1T timing</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_prefer_write</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1 = Bank selector prefers writes over reads</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_max_rank_rd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3c</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr_wr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr_addr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr_data</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1fffe00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_reg_mr_wr_busy</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:25</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr_type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:26</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Indicates whether the Mode register operation is read or write 1 = read 0 = write</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr_rdata_valid</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_param_reg4@0XF8006024</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Parameters register 4</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_init_param">Register (<A href=#mod___slcr> slcr </A>)DRAM_init_param</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_init_param</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006028</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_final_wait_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_pre_ocd_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>780</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_mrd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_init_param@0XF8006028</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2007</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM initialization parameters register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_EMR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_EMR_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800602C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_emr2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_emr3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_EMR_reg@0XF800602C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM EMR2, EMR3 access register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_EMR_MR_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_EMR_MR_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_EMR_MR_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006030</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>930</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>930</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_emr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_EMR_MR_reg@0XF8006030</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>40930</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM EMR, MR access register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_burst8_rdwr">Register (<A href=#mod___slcr> slcr </A>)DRAM_burst8_rdwr</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_burst8_rdwr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_burst_rdwr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_pre_cke_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>167</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1670</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_post_cke_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_burstchop</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>28:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Feature not supported. When 1, Controller is out in burstchop mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_burst8_rdwr@0XF8006034</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>13ff3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>11674</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM burst 8 read/write register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_disable_DQ">Register (<A href=#mod___slcr> slcr </A>)DRAM_disable_DQ</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_disable_DQ</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006038</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_force_low_pri_n</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_dq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_debug_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Not Applicable in this PHY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_level_start</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Not Applicable in this PHY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_level_start</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Not Applicable in this PHY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dq0_wait_t</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Not Applicable in this PHY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_disable_DQ@0XF8006038</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fc3</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM Disable DQ register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_addr_map_bank">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_bank</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_addr_map_bank</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800603C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_bank_b0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_bank_b1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>70</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_bank_b2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>700</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_addr_map_bank@0XF800603C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>777</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Selects the address bits used as DRAM bank address bits</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_addr_map_col">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_col</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_addr_map_col</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006040</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b9</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f00000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b10</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_col_b11</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f0000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_addr_map_col@0XF8006040</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>fff00000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Selects the address bits used as DRAM column address bits</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_addr_map_row">Register (<A href=#mod___slcr> slcr </A>)DRAM_addr_map_row</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_addr_map_row</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006044</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b2_11</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b12</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b13</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b14</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f00000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_addrmap_row_b15</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_addr_map_row@0XF8006044</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ff66666</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Selects the address bits used as DRAM row address bits</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DRAM_ODT_reg">Register (<A href=#mod___slcr> slcr </A>)DRAM_ODT_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRAM_ODT_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006048</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rank0_rd_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rank0_wr_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>38</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rank1_rd_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rank1_wr_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_local_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_local_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_idle_local_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>30000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rank2_rd_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rank2_wr_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rank3_rd_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rank3_wr_odt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>29:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>38000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DRAM_ODT_reg@0XF8006048</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3c248</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DRAM ODT register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_cmd_timeout_rddata_cpt">Register (<A href=#mod___slcr> slcr </A>)phy_cmd_timeout_rddata_cpt</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_cmd_timeout_rddata_cpt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006050</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_cmd_to_data</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Not used in DFI PHY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_cmd_to_data</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Not used in DFI PHY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdc_we_to_re_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdc_fifo_rst_disable</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_use_fixed_re</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdc_fifo_rst_err_cnt_clr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dis_phy_ctrl_rstn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_clk_stall_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1 = stall clock, for DLL aging control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_num_of_dq0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_num_of_dq0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>70000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_cmd_timeout_rddata_cpt@0XF8006050</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff0f8fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>77010800</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY command time out and read data capture FIFO register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DLL_calib">Register (<A href=#mod___slcr> slcr </A>)DLL_calib</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DLL_calib</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006058</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dll_calib_to_min_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused in DFI Controller.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dll_calib_to_max_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused in DFI Controller.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_dll_calib</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DLL_calib@0XF8006058</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>101</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DLL calibration register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ODT_delay_hold">Register (<A href=#mod___slcr> slcr </A>)ODT_delay_hold</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ODT_delay_hold</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800605C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rd_odt_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UNUSED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_wr_odt_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rd_odt_hold</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Unused</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_wr_odt_hold</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ODT_delay_hold@0XF800605C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>5003</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ODT delay and ODT hold register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ctrl_reg1">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ctrl_reg1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006060</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_pageclose</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_lpr_num_entries</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7e</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3e</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_auto_pre_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_refresh_update_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_wc</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When 1, disable Write Combine</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_collision_page_opt</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_selfref_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If 1, then the controller will put the DRAM into self refresh when the transaction store is empty.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ctrl_reg1@0XF8006060</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>17ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3e</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Controller register 1</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ctrl_reg2">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg2</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ctrl_reg2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006064</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_go2critical_hysteresis</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1fe0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_go2critical_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ctrl_reg2@0XF8006064</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>21fe0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>20000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Controller register 2</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ctrl_reg3">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg3</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ctrl_reg3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006068</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_wrlvl_ww</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>41</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>41</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rdlvl_rr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>41</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_wlmrd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>28</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>280000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ctrl_reg3@0XF8006068</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>284141</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Controller register 3</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ctrl_reg4">Register (<A href=#mod___slcr> slcr </A>)ctrl_reg4</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ctrl_reg4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800606C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dfi_t_ctrlupd_interval_min_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dfi_t_ctrlupd_interval_max_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>16</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ctrl_reg4@0XF800606C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1610</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Controller register 4</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_REFRESH_TIMER01">Register (<A href=#mod___slcr> slcr </A>)CHE_REFRESH_TIMER01</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_REFRESH_TIMER01</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060A0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>refresh_timer0_start_value_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>refresh_timer1_start_value_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_REFRESH_TIMER01@0XF80060A0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>8000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>CHE_REFRESH_TIMER01</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_T_ZQ">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_T_ZQ</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060A4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_auto_zq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_ddr3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_mod</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_zq_long_nop</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_zq_short_nop</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_T_ZQ@0XF80060A4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>10200802</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ZQ parameters register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_T_ZQ_Short_Interval_Reg">Register (<A href=#mod___slcr> slcr </A>)CHE_T_ZQ_Short_Interval_Reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_T_ZQ_Short_Interval_Reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>t_zq_short_interval_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c845</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c845</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dram_rstn_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>67</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6700000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_T_ZQ_Short_Interval_Reg@0XF80060A8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>670c845</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Misc parameters register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="deep_pwrdwn_reg">Register (<A href=#mod___slcr> slcr </A>)deep_pwrdwn_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>deep_pwrdwn_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>deeppowerdown_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>deeppowerdown_to_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1fe</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1fe</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>deep_pwrdwn_reg@0XF80060AC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1fe</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Deep powerdown register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="reg_2c">Register (<A href=#mod___slcr> slcr </A>)reg_2c</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_2c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dfi_wrlvl_max_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>fff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dfi_rdlvl_max_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>fff000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_reg_twrlvl_max_error</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_reg_trdlvl_max_error</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:25</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_wr_level_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:26</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_rd_dqs_gate_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_rd_data_eye_train</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>28:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>reg_2c@0XF80060B0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1cffffff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Training control register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="reg_2d">Register (<A href=#mod___slcr> slcr </A>)reg_2d</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_2d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_2t_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_skip_ocd</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_pre_bypass</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>reg_2d@0XF80060B4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Misc Debug register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="dfi_timing">Register (<A href=#mod___slcr> slcr </A>)dfi_timing</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>dfi_timing</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060B8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_rddata_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_ctrlup_min</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7fe0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dfi_t_ctrlup_max</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>dfi_timing@0XF80060B8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200066</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DFI timing register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_ECC_CONTROL_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_CONTROL_REG_OFFSET</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_ECC_CONTROL_REG_OFFSET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Clear_Uncorrectable_DRAM_ECC_error</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Clear_Correctable_DRAM_ECC_error</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ECC error clear register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_CORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_CORR_ECC_LOG_REG_OFFSET</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_CORR_ECC_LOG_REG_OFFSET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060C8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CORR_ECC_LOG_VALID</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ECC_CORRECTED_BIT_NUM</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fe</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ECC error correction register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_UNCORR_ECC_LOG_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_UNCORR_ECC_LOG_REG_OFFSET</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_UNCORR_ECC_LOG_REG_OFFSET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060DC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNCORR_ECC_LOG_VALID</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31).</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ECC unrecoverable error status register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="CHE_ECC_STATS_REG_OFFSET">Register (<A href=#mod___slcr> slcr </A>)CHE_ECC_STATS_REG_OFFSET</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHE_ECC_STATS_REG_OFFSET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060F0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STAT_NUM_CORR_ERR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58).</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STAT_NUM_UNCORR_ERR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58).</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CHE_ECC_STATS_REG_OFFSET@0XF80060F0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ECC error count register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ECC_scrub">Register (<A href=#mod___slcr> slcr </A>)ECC_scrub</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ECC_scrub</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80060F4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_ecc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_scrub</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ECC_scrub@0XF80060F4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>8</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>ECC mode/scrub register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_rcvr_enable">Register (<A href=#mod___slcr> slcr </A>)phy_rcvr_enable</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_rcvr_enable</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006114</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dif_on</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dif_off</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_rcvr_enable@0XF8006114</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Phy receiver enable register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PHY_Config</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006118</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_data_slice_in_use</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>RESERVED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>RESERVED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>RESERVED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_tx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_rx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_shift_dq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7fc0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_err_clr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dq_offset</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PHY_Config@0XF8006118</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>40000001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PHY_Config</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800611C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_data_slice_in_use</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>RESERVED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>RESERVED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>RESERVED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_tx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_rx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_shift_dq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7fc0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_err_clr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dq_offset</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PHY_Config@0XF800611C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>40000001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PHY_Config</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006120</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_data_slice_in_use</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>RESERVED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>RESERVED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>RESERVED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_tx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_rx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_shift_dq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7fc0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_err_clr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dq_offset</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PHY_Config@0XF8006120</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>40000001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="PHY_Config">Register (<A href=#mod___slcr> slcr </A>)PHY_Config</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PHY_Config</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006124</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_data_slice_in_use</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rdlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>RESERVED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>RESERVED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_inc_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>RESERVED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_tx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_board_lpbk_rx</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_shift_dq</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7fc0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_err_clr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dq_offset</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>PHY_Config@0XF8006124</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7fffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>40000001</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800612C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used by Write Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23c00</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used Gate Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_init_ratio@0XF800612C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>23c00</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006130</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used by Write Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8a</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used Gate Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_init_ratio@0XF8006130</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>22800</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006134</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used by Write Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22c00</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used Gate Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_init_ratio@0XF8006134</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>22c00</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_init_ratio">Register (<A href=#mod___slcr> slcr </A>)phy_init_ratio</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006138</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wrlvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used by Write Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_gatelvl_init_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>92</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The user programmable init ratio used Gate Leveling FSM</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_init_ratio@0XF8006138</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>24800</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY init ratio register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_rd_dqs_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006140</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_rd_dqs_cfg@0XF8006140</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_rd_dqs_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006144</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_rd_dqs_cfg@0XF8006144</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_rd_dqs_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006148</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_rd_dqs_cfg@0XF8006148</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_rd_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_rd_dqs_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_rd_dqs_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800614C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_rd_dqs_cfg@0XF800614C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>35</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY read DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_wr_dqs_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006154</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>77</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>77</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_wr_dqs_cfg@0XF8006154</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>77</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_wr_dqs_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006158</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_wr_dqs_cfg@0XF8006158</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_wr_dqs_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800615C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_wr_dqs_cfg@0XF800615C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_wr_dqs_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_wr_dqs_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_wr_dqs_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006160</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>75</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>75</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_dqs_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_wr_dqs_cfg@0XF8006160</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>75</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write DQS configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_we_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006168</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_we_cfg@0XF8006168</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>e4</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY fifo write enable configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_we_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800616C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_we_cfg@0XF800616C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY fifo write enable configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_we_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006170</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_we_cfg@0XF8006170</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>e0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY fifo write enable configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="phy_we_cfg">Register (<A href=#mod___slcr> slcr </A>)phy_we_cfg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>phy_we_cfg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006174</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e7</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value to be used when fifo_we_X_force_mode is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_fifo_we_in_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>phy_we_cfg@0XF8006174</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>e7</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY fifo write enable configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>wr_data_slv</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800617C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>b7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>b7</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>wr_data_slv@0XF800617C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>b7</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write data slave ratio configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>wr_data_slv</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006180</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>bc</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>bc</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>wr_data_slv@0XF8006180</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>bc</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write data slave ratio configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>wr_data_slv</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006184</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>bc</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>bc</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>wr_data_slv@0XF8006184</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>bc</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write data slave ratio configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="wr_data_slv">Register (<A href=#mod___slcr> slcr </A>)wr_data_slv</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>wr_data_slv</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006188</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>b5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>b5</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_data_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>wr_data_slv@0XF8006188</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>b5</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>PHY write data slave ratio configuration register for data slice 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="reg_64">Register (<A href=#mod___slcr> slcr </A>)reg_64</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_64</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006190</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_loopback</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Loopback testing. 1: enable, 0: disable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bl2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved for future Use.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_at_spd_atpg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_enable</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_force_err</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_bist_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_invert_clkout</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_all_dq_mpr_rd_resp</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_sel_logic</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_ctrl_slave_ratio</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffc00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_ctrl_slave_force</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_ctrl_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>27:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fe00000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_use_rank0_delays</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>28:28</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_lpddr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>29:29</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_cmd_latency</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>30:30</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If set to 1, command comes to phy_ctrl through a flop.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_int_lpbk</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:31</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>reg_64@0XF8006190</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>10040080</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Training control register (2)</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="reg_65">Register (<A href=#mod___slcr> slcr </A>)reg_65</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_65</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006194</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_wr_rl_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_rd_rl_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dll_lock_diff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3c00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3c00</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_use_wr_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_use_rd_dqs_gate_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_use_rd_data_eye_level</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_dis_calib_rst</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_phy_ctrl_slave_delay</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>reg_65@0XF8006194</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1fc82</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Training control register (3)</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="page_mask">Register (<A href=#mod___slcr> slcr </A>)page_mask</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>page_mask</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006204</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_page_addr_mask</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>page_mask@0XF8006204</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Page mask register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_wr_port</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006208</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_rmw_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_wr_port@0XF8006208</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>803ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_wr_port</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800620C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_rmw_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_wr_port@0XF800620C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>803ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_wr_port</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006210</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_rmw_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_wr_port@0XF8006210</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>803ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_wr_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_wr_port</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_wr_port</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006214</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Write Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_wr_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_rmw_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_wr_port@0XF8006214</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>803ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for write port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_rd_port</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006218</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_set_hpr_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable reads to be generated as HPR for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_rd_port@0XF8006218</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_rd_port</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800621C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_set_hpr_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable reads to be generated as HPR for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_rd_port@0XF800621C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_rd_port</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006220</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_set_hpr_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable reads to be generated as HPR for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_rd_port@0XF8006220</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="axi_priority_rd_port">Register (<A href=#mod___slcr> slcr </A>)axi_priority_rd_port</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>axi_priority_rd_port</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006224</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_pri_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_aging_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable aging for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_disable_urgent_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable urgent for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_dis_page_match_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable the page match feature.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_arb_set_hpr_rd_portn</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable reads to be generated as HPR for this Read Port.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>axi_priority_rd_port@0XF8006224</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f03ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>3ff</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>AXI Priority control for read port 0.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="lpddr_ctrl0">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>lpddr_ctrl0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_lpddr2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_per_bank_refresh</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_derate_enable</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr4_margin</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UNUSED</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>lpddr_ctrl0@0XF80062A8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff7</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>LPDDR2 Control 0 Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="lpddr_ctrl1">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>lpddr_ctrl1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_mr4_read_interval</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>lpddr_ctrl1@0XF80062AC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>LPDDR2 Control 1 Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="lpddr_ctrl2">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl2</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>lpddr_ctrl2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_min_stable_clock_x1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_idle_after_reset_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>12</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>120</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_t_mrw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>5</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>lpddr_ctrl2@0XF80062B0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>5125</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>LPDDR2 Control 2 Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="lpddr_ctrl3">Register (<A href=#mod___slcr> slcr </A>)lpddr_ctrl3</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>lpddr_ctrl3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80062B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_max_auto_init_x1024</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>a6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>a6</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dev_zqinit_x32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3ff00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>12</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>lpddr_ctrl3@0XF80062B4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>12a6</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>LPDDR2 Control 3 Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>POLL ON DCI STATUS</H1>
-<H2><a name="DDRIOB_DCI_STATUS">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_STATUS</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DCI_STATUS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B74</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DONE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI done signal</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DCI_STATUS@0XF8000B74</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>tobe</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>UNLOCK DDR</H1>
-<H2><a name="ddrc_ctrl">Register (<A href=#mod___slcr> slcr </A>)ddrc_ctrl</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_ctrl</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_soft_rstb</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_powerdown_en</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_data_bus_width</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_burst8_refresh</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_rdwr_idle_gap</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_rd_bypass</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_act_bypass</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:15</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reg_ddrc_dis_auto_refresh</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>ddrc_ctrl@0XF8006000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>81</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRC Control Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>CHECK DDR STATUS</H1>
-<H2><a name="mode_sts_reg">Register (<A href=#mod___slcr> slcr </A>)mode_sts_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>mode_sts_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8006054</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ddrc_reg_operating_mode</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>mode_sts_reg@0XF8006054</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>tobe</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-</TABLE>
-<P>
-<H2><a name="ps7_mio_init_data_1_0">ps7_mio_init_data_1_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_UNLOCK">
-SLCR_UNLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#GPIOB_CTRL">
-GPIOB_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>GPIOB control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_ADDR0">
-DDRIOB_ADDR0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB Address 0 Configuartion Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_ADDR1">
-DDRIOB_ADDR1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B44</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB Address 1 Configuration Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DATA0">
-DDRIOB_DATA0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B48</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB Data 0 Configuration Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DATA1">
-DDRIOB_DATA1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B4C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB Data 1 Configuration Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DIFF0">
-DDRIOB_DIFF0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B50</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB Differential DQS 0 Configuration Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DIFF1">
-DDRIOB_DIFF1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B54</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB Differential DQS 1 Configuration Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_CLOCK">
-DDRIOB_CLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B58</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB Differential Clock Configuration Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DRIVE_SLEW_ADDR">
-DDRIOB_DRIVE_SLEW_ADDR
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B5C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB Drive Slew Address Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DRIVE_SLEW_DATA">
-DDRIOB_DRIVE_SLEW_DATA
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB Drive Slew Data Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DRIVE_SLEW_DIFF">
-DDRIOB_DRIVE_SLEW_DIFF
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B64</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB Drive Slew Differential Strobe Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DRIVE_SLEW_CLOCK">
-DDRIOB_DRIVE_SLEW_CLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B68</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB Drive Slew Clcok Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DDR_CTRL">
-DDRIOB_DDR_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B6C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB DDR Control Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DCI_CTRL">
-DDRIOB_DCI_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB DCI configuration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DCI_CTRL">
-DDRIOB_DCI_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB DCI configuration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DCI_CTRL">
-DDRIOB_DCI_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB DCI configuration</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_00">
-MIO_PIN_00
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000700</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_01">
-MIO_PIN_01
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000704</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_02">
-MIO_PIN_02
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000708</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 2</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_03">
-MIO_PIN_03
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800070C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 3</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_04">
-MIO_PIN_04
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000710</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 4</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_05">
-MIO_PIN_05
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000714</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 5</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_06">
-MIO_PIN_06
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000718</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 6</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_07">
-MIO_PIN_07
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800071C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 7</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_08">
-MIO_PIN_08
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000720</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 8</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_09">
-MIO_PIN_09
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000724</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 9</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_10">
-MIO_PIN_10
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000728</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 10</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_11">
-MIO_PIN_11
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800072C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 11</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_12">
-MIO_PIN_12
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000730</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 12</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_13">
-MIO_PIN_13
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000734</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 13</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_14">
-MIO_PIN_14
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000738</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 14</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_15">
-MIO_PIN_15
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800073C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 15</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_16">
-MIO_PIN_16
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000740</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 16</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_17">
-MIO_PIN_17
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000744</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 17</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_18">
-MIO_PIN_18
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000748</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 18</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_19">
-MIO_PIN_19
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800074C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 19</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_20">
-MIO_PIN_20
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000750</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 20</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_21">
-MIO_PIN_21
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000754</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 21</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_22">
-MIO_PIN_22
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000758</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 22</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_23">
-MIO_PIN_23
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800075C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 23</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_24">
-MIO_PIN_24
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000760</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 24</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_25">
-MIO_PIN_25
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000764</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 25</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_26">
-MIO_PIN_26
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000768</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 26</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_27">
-MIO_PIN_27
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800076C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 27</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_28">
-MIO_PIN_28
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000770</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 28</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_29">
-MIO_PIN_29
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000774</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 29</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_30">
-MIO_PIN_30
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000778</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 30</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_31">
-MIO_PIN_31
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800077C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 31</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_32">
-MIO_PIN_32
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000780</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 32</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_33">
-MIO_PIN_33
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000784</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_34">
-MIO_PIN_34
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000788</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 34</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_35">
-MIO_PIN_35
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800078C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 35</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_36">
-MIO_PIN_36
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000790</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 36</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_37">
-MIO_PIN_37
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000794</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 37</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_38">
-MIO_PIN_38
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000798</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 38</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_39">
-MIO_PIN_39
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800079C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 39</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_40">
-MIO_PIN_40
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 40</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_41">
-MIO_PIN_41
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 41</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_42">
-MIO_PIN_42
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 42</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_43">
-MIO_PIN_43
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 43</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_44">
-MIO_PIN_44
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 44</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_45">
-MIO_PIN_45
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 45</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_46">
-MIO_PIN_46
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 46</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_47">
-MIO_PIN_47
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007BC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 47</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_48">
-MIO_PIN_48
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 48</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_49">
-MIO_PIN_49
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 49</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_50">
-MIO_PIN_50
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 50</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_51">
-MIO_PIN_51
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007CC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 51</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_52">
-MIO_PIN_52
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007D0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 52</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MIO_PIN_53">
-MIO_PIN_53
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007D4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>MIO Control for Pin 53</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SD0_WP_CD_SEL">
-SD0_WP_CD_SEL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000830</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO 0 WP CD select register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_LOCK">
-SLCR_LOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_mio_init_data_1_0">ps7_mio_init_data_1_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>SLCR SETTINGS</H1>
-<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_UNLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNLOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_UNLOCK@0XF8000008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>OCM REMAPPING</H1>
-<H2><a name="GPIOB_CTRL">Register (<A href=#mod___slcr> slcr </A>)GPIOB_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GPIOB_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VREF_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables VREF internal generator</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VREF_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables internal pullup. 0 - no pullup. 1 - pullup.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLK_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables internal pullup. 0 - no pullup. 1 - pullup.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SRSTN_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables internal pullup. 0 - no pullup. 1 - pullup.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>GPIOB_CTRL@0XF8000B00</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>303</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>GPIOB control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DDRIOB SETTINGS</H1>
-<H2><a name="DDRIOB_ADDR0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_ADDR0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCR_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_ADDR0@0XF8000B40</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB Address 0 Configuartion Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_ADDR1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_ADDR1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_ADDR1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B44</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCR_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_ADDR1@0XF8000B44</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB Address 1 Configuration Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DATA0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B48</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCR_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DATA0@0XF8000B48</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>672</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB Data 0 Configuration Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DATA1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B4C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCR_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DATA1@0XF8000B4C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>672</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB Data 1 Configuration Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DIFF0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B50</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCR_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DIFF0@0XF8000B50</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>674</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB Differential DQS 0 Configuration Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DIFF1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B54</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCR_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DIFF1@0XF8000B54</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>674</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB Differential DQS 1 Configuration Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_CLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_CLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B58</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_POWER</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INP_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCI_UPDATE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri State Termination Enabled 0 - disabled 1 - enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DCR_TYPE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OUTPUT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>enables pullup on output 0 - no pullup 1 - pullup enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_CLOCK@0XF8000B58</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB Differential Clock Configuration Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DRIVE_SLEW_ADDR">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_ADDR</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DRIVE_SLEW_ADDR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B5C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRIVE_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Programs the DDRIO drive strength for the P devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRIVE_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Programs the DDRIO drive strength for the N devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLEW_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Programs the DDRIO slew rate for the P devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLEW_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>180000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Programs the DDRIO slew rate for the N devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GTL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Test Control 000 - Normal Operation 001 : 111 - Test Mode</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RTERM</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Program the rterm</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>18c61c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB Drive Slew Address Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DRIVE_SLEW_DATA">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DATA</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DRIVE_SLEW_DATA</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRIVE_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Programs the DDRIO drive strength for the P devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRIVE_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Programs the DDRIO drive strength for the N devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLEW_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Programs the DDRIO slew rate for the P devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLEW_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Programs the DDRIO slew rate for the N devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GTL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Test Control 000 - Normal Operation 001 : 111 - Test Mode</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RTERM</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Program the rterm</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DRIVE_SLEW_DATA@0XF8000B60</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>f9861c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB Drive Slew Data Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DRIVE_SLEW_DIFF">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_DIFF</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DRIVE_SLEW_DIFF</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B64</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRIVE_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Programs the DDRIO drive strength for the P devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRIVE_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Programs the DDRIO drive strength for the N devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLEW_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Programs the DDRIO slew rate for the P devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLEW_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Programs the DDRIO slew rate for the N devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GTL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Test Control 000 - Normal Operation 001 : 111 - Test Mode</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RTERM</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Program the rterm</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>f9861c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB Drive Slew Differential Strobe Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DRIVE_SLEW_CLOCK">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DRIVE_SLEW_CLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DRIVE_SLEW_CLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B68</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRIVE_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Programs the DDRIO drive strength for the P devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRIVE_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Programs the DDRIO drive strength for the N devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLEW_P</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>18000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Programs the DDRIO slew rate for the P devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLEW_N</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>f80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Programs the DDRIO slew rate for the N devices</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>GTL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Test Control 000 - Normal Operation 001 : 111 - Test Mode</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RTERM</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:27</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f8000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Program the rterm</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>f9861c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB Drive Slew Clcok Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DDR_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DDR_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DDR_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B6C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VREF_INT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables VREF internal generator</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VREF_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1e</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VREF_EXT_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>60</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VREF_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>REFIO_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>REFIO_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DRST_B_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CKE_PULLUP_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>14:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DDR_CTRL@0XF8000B6C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>73ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>260</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB DDR Control Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ASSERT RESET</H1>
-<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DCI_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>At least toggle once to initialise flops in DCI system</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VRN_OUT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>VRN output value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>21</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>21</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB DCI configuration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DEASSERT RESET</H1>
-<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DCI_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>At least toggle once to initialise flops in DCI system</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VRN_OUT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>VRN output value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>21</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB DCI configuration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DCI_CTRL">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DCI_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DCI_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B70</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RESET</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>At least toggle once to initialise flops in DCI system</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>1 if any iob's use a terminate type, or if dci test block used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VRP_TRI</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>VRP tristate value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VRN_TRI</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>VRN tristate value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VRP_OUT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>VRP output value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>VRN_OUT</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>VRN output value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>NREF_OPT1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>NREF_OPT2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>700</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>NREF_OPT4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PREF_OPT1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PREF_OPT2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UPDATE_CONTROL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DCI Update</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INIT_COMPLETE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>test Internal to IO bank</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TST_CLK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Emulate DCI clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TST_HLN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:23</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Emulate comparator output (VRN)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TST_HLP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Emulate comparator output (VRP)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TST_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>25:25</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Emulate Reset</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>INT_DCI_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>26:26</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Need explanation here</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DCI_CTRL@0XF8000B70</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>7ffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>823</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB DCI configuration</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MIO PROGRAMMING</H1>
-<H2><a name="MIO_PIN_00">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_00</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_00</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000700</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_00@0XF8000700</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 0</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_01">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_01</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_01</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000704</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_01@0XF8000704</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 1</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_02">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_02</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_02</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000708</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_02@0XF8000708</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 2</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_03">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_03</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_03</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800070C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_03@0XF800070C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 3</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_04">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_04</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_04</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000710</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_04@0XF8000710</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 4</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_05">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_05</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_05</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000714</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_05@0XF8000714</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 5</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_06">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_06</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_06</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000718</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_06@0XF8000718</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 6</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_07">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_07</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_07</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800071C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_07@0XF800071C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 7</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_08">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_08</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_08</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000720</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1]</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_08@0XF8000720</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>702</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 8</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_09">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_09</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_09</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000724</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_09@0XF8000724</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 9</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_10">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_10</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_10</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000728</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_10@0XF8000728</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1640</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 10</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_11">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_11</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_11</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800072C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_11@0XF800072C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1640</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 11</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_12">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_12</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_12</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000730</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_12@0XF8000730</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1640</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 12</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_13">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_13</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_13</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000734</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_13@0XF8000734</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1640</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 13</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_14">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_14</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_14</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000738</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_14@0XF8000738</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 14</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_15">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_15</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_15</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800073C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>600</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_15@0XF800073C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1600</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 15</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_16">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_16</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_16</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000740</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_16@0XF8000740</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 16</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_17">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_17</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_17</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000744</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_17@0XF8000744</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 17</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_18">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_18</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_18</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000748</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_18@0XF8000748</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 18</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_19">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_19</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_19</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800074C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_19@0XF800074C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 19</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_20">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_20</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_20</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000750</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_20@0XF8000750</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 20</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_21">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_21</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_21</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000754</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_21@0XF8000754</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2902</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 21</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_22">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_22</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_22</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000758</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_22@0XF8000758</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 22</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_23">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_23</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_23</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800075C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_23@0XF800075C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 23</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_24">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_24</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_24</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000760</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_24@0XF8000760</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 24</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_25">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_25</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_25</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000764</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_25@0XF8000764</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 25</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_26">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_26</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_26</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000768</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_26@0XF8000768</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 26</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_27">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_27</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_27</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800076C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_27@0XF800076C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>903</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 27</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_28">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_28</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_28</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000770</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_28@0XF8000770</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 28</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_29">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_29</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_29</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000774</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_29@0XF8000774</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>305</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 29</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_30">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_30</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_30</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000778</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_30@0XF8000778</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 30</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_31">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_31</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_31</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800077C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_31@0XF800077C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>305</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 31</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_32">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_32</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_32</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000780</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_32@0XF8000780</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 32</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_33">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_33</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_33</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000784</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_33@0XF8000784</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 33</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_34">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_34</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_34</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000788</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_34@0XF8000788</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 34</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_35">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_35</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_35</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800078C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_35@0XF800078C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 35</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_36">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_36</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_36</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000790</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_36@0XF8000790</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>305</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 36</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_37">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_37</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_37</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000794</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_37@0XF8000794</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 37</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_38">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_38</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_38</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000798</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_38@0XF8000798</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 38</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_39">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_39</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_39</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF800079C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_39@0XF800079C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>304</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 39</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_40">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_40</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_40</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_40@0XF80007A0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 40</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_41">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_41</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_41</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_41@0XF80007A4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 41</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_42">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_42</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_42</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007A8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_42@0XF80007A8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 42</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_43">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_43</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_43</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007AC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_43@0XF80007AC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 43</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_44">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_44</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_44</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_44@0XF80007B0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 44</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_45">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_45</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_45</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_45@0XF80007B4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>380</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 45</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_46">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_46</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_46</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007B8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_46@0XF80007B8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>1200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 46</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_47">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_47</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_47</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007BC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_47@0XF80007BC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f01</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>201</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 47</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_48">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_48</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_48</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_48@0XF80007C0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2e0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 48</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_49">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_49</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_49</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_49@0XF80007C4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2e1</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 49</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_50">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_50</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_50</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007C8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_50@0XF80007C8</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 50</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_51">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_51</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_51</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007CC</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_51@0XF80007CC</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 51</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_52">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_52</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_52</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007D0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_52@0XF80007D0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 52</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="MIO_PIN_53">Register (<A href=#mod___slcr> slcr </A>)MIO_PIN_53</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MIO_PIN_53</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF80007D4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TRI_ENABLE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Tri-state enable, active high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L0_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L1_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L2_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>L3_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Speed</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IO_Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>e00</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PULLUP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DisableRcvr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MIO_PIN_53@0XF80007D4</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>200</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>MIO Control for Pin 53</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="SD0_WP_CD_SEL">Register (<A href=#mod___slcr> slcr </A>)SD0_WP_CD_SEL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SD0_WP_CD_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000830</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SDIO0_WP_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>37</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>37</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SDIO0_CD_SEL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3f0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2f</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2f0000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SD0_WP_CD_SEL@0XF8000830</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3f003f</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>2f0037</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SDIO 0 WP CD select register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>LOCK IT BACK</H1>
-<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_LOCK@0XF8000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-</TABLE>
-<P>
-<H2><a name="ps7_peripherals_init_data_1_0">ps7_peripherals_init_data_1_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_UNLOCK">
-SLCR_UNLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DATA0">
-DDRIOB_DATA0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B48</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB Data 0 Configuration Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DATA1">
-DDRIOB_DATA1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B4C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB Data 1 Configuration Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DIFF0">
-DDRIOB_DIFF0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B50</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB Differential DQS 0 Configuration Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DDRIOB_DIFF1">
-DDRIOB_DIFF1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B54</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>DDRIOB Differential DQS 1 Configuration Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_LOCK">
-SLCR_LOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Baud_rate_divider_reg0">
-Baud_rate_divider_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>baud rate divider register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Baud_rate_gen_reg0">
-Baud_rate_gen_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud rate divider register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Control_reg0">
-Control_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART Control register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#mode_reg0">
-mode_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART Mode register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Baud_rate_divider_reg0">
-Baud_rate_divider_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>baud rate divider register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Baud_rate_gen_reg0">
-Baud_rate_gen_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud rate divider register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Control_reg0">
-Control_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART Control register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#mode_reg0">
-mode_reg0
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>UART Mode register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#Config_reg">
-Config_reg
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000D000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SPI configuration register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#CTRL">
-CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8007000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#DIRM_1">
-DIRM_1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A244</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Direction mode configuration register: Configures bank 1 for direction mode, either input or output</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MASK_DATA_1_LSW">
-MASK_DATA_1_LSW
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#OEN_1">
-OEN_1
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A248</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Output enable register: Configures the output enables of bank 1</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MASK_DATA_1_LSW">
-MASK_DATA_1_LSW
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#MASK_DATA_1_LSW">
-MASK_DATA_1_LSW
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_peripherals_init_data_1_0">ps7_peripherals_init_data_1_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>SLCR SETTINGS</H1>
-<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_UNLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNLOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_UNLOCK@0XF8000008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>DDR TERM/IBUF_DISABLE_MODE SETTINGS</H1>
-<H2><a name="DDRIOB_DATA0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DATA0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B48</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DATA0@0XF8000B48</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB Data 0 Configuration Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DATA1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DATA1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DATA1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B4C</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DATA1@0XF8000B4C</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB Data 1 Configuration Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DIFF0">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DIFF0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B50</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DIFF0@0XF8000B50</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB Differential DQS 0 Configuration Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="DDRIOB_DIFF1">Register (<A href=#mod___slcr> slcr </A>)DDRIOB_DIFF1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DDRIOB_DIFF1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000B54</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IBUF_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TERM_DISABLE_MODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DDRIOB_DIFF1@0XF8000B54</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>180</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>DDRIOB Differential DQS 1 Configuration Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>LOCK IT BACK</H1>
-<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_LOCK@0XF8000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>SRAM/NOR SET OPMODE</H1>
-<H1>UART REGISTERS</H1>
-<H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Baud_rate_divider_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>BDIV</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Baud_rate_divider_reg0@0XE0001034</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>baud rate divider register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Baud_rate_gen_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CD</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Baud_rate_gen_reg0@0XE0001018</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Baud rate divider register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Control_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STPBRK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Stop transmitter break. 1 = stop transmission of the break.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STTBRK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RSTTO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Restart receiver timeout counter 1 = receiver timeout counter is restarted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXDIS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Transmit disable. 1, the transmitter is disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXEN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXDIS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Receive disable. 1= receiver is enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXEN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXRES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXRES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Control_reg0@0XE0001000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>17</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>UART Control register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>mode_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0001004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IRMODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UCLKEN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHMODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>300</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>NBSTOP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PAR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>38</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>mode_reg0@0XE0001004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>UART Mode register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Baud_rate_divider_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_divider_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Baud_rate_divider_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000034</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>BDIV</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Baud_rate_divider_reg0@0XE0000034</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>6</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>baud rate divider register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Baud_rate_gen_reg0">Register (<A href=#mod___slcr> slcr </A>)Baud_rate_gen_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Baud_rate_gen_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000018</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CD</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Baud_rate_gen_reg0@0XE0000018</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>7c</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Baud rate divider register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="Control_reg0">Register (<A href=#mod___slcr> slcr </A>)Control_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Control_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STPBRK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Stop transmitter break. 1 = stop transmission of the break.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>STTBRK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:7</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RSTTO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>6:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>40</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Restart receiver timeout counter 1 = receiver timeout counter is restarted</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXDIS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:5</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Transmit disable. 1, the transmitter is disabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXEN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXDIS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Receive disable. 1= receiver is enabled</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXEN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>TXRES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>RXRES</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Control_reg0@0XE0000000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>1ff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>17</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>UART Control register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="mode_reg0">Register (<A href=#mod___slcr> slcr </A>)mode_reg0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>mode_reg0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE0000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>IRMODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UCLKEN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHMODE</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>300</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>NBSTOP</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PAR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>5:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>38</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CHRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>6</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CLKS</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>mode_reg0@0XE0000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>fff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>20</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>UART Mode register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>QSPI REGISTERS</H1>
-<H2><a name="Config_reg">Register (<A href=#mod___slcr> slcr </A>)Config_reg</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Config_reg</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000D000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>Holdb_dr</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:19</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>Config_reg@0XE000D000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>80000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>80000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SPI configuration register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>PL POWER ON RESET REGISTERS</H1>
-<H2><a name="CTRL">Register (<A href=#mod___slcr> slcr </A>)CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8007000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>PCFG_POR_CNT_4K</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>29:29</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>CTRL@0XF8007000</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>20000000</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>SMC TIMING CALCULATION REGISTER UPDATE</H1>
-<H1>NAND SET CYCLE</H1>
-<H1>OPMODE</H1>
-<H1>DIRECT COMMAND</H1>
-<H1>SRAM/NOR CS0 SET CYCLE</H1>
-<H1>DIRECT COMMAND</H1>
-<H1>NOR CS0 BASE ADDRESS</H1>
-<H1>SRAM/NOR CS1 SET CYCLE</H1>
-<H1>DIRECT COMMAND</H1>
-<H1>NOR CS1 BASE ADDRESS</H1>
-<H1>USB RESET</H1>
-<H1>USB0 RESET</H1>
-<H1>DIR MODE BANK 0</H1>
-<H1>DIR MODE BANK 1</H1>
-<H2><a name="DIRM_1">Register (<A href=#mod___slcr> slcr </A>)DIRM_1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIRM_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A244</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DIRECTION_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Direction mode for bank 1 0 = input 1 = output Each bit configures the corresponding pin within the 32-bit bank</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>DIRM_1@0XE000A244</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Direction mode configuration register: Configures bank 1 for direction mode, either input or output</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>bfff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>bfff0000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MASK_DATA_1_LSW@0XE000A008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>bfff4000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE BANK 0</H1>
-<H1>OUTPUT ENABLE BANK 1</H1>
-<H2><a name="OEN_1">Register (<A href=#mod___slcr> slcr </A>)OEN_1</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OEN_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A248</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>OP_ENABLE_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Output enables for bank 1 0 = disabled 1 = enabled Each bit configures the corresponding pin within the 32-bit bank</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>OEN_1@0XE000A248</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>3fffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Output enable register: Configures the output enables of bank 1</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>bfff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>bfff0000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MASK_DATA_1_LSW@0XE000A008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>bfff0000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H2><a name="MASK_DATA_1_LSW">Register (<A href=#mod___slcr> slcr </A>)MASK_DATA_1_LSW</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XE000A008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>MASK_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>bfff</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>bfff0000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>DATA_1_LSW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>4000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>MASK_DATA_1_LSW@0XE000A008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>bfff4000</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>USB1 RESET</H1>
-<H1>DIR MODE BANK 0</H1>
-<H1>DIR MODE BANK 1</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE BANK 0</H1>
-<H1>OUTPUT ENABLE BANK 1</H1>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>ENET RESET</H1>
-<H1>ENET0 RESET</H1>
-<H1>DIR MODE BANK 0</H1>
-<H1>DIR MODE BANK 1</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE BANK 0</H1>
-<H1>OUTPUT ENABLE BANK 1</H1>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>ENET1 RESET</H1>
-<H1>DIR MODE BANK 0</H1>
-<H1>DIR MODE BANK 1</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE BANK 0</H1>
-<H1>OUTPUT ENABLE BANK 1</H1>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>I2C RESET</H1>
-<H1>I2C0 RESET</H1>
-<H1>DIR MODE GPIO BANK0</H1>
-<H1>DIR MODE GPIO BANK1</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE</H1>
-<H1>OUTPUT ENABLE</H1>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>I2C1 RESET</H1>
-<H1>DIR MODE GPIO BANK0</H1>
-<H1>DIR MODE GPIO BANK1</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>OUTPUT ENABLE</H1>
-<H1>OUTPUT ENABLE</H1>
-<H1>MASK_DATA_0_LSW LOW BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW LOW BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW LOW BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW LOW BANK [53:48]</H1>
-<H1>ADD 1 MS DELAY</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>MASK_DATA_0_MSW HIGH BANK [31:16]</H1>
-<H1>MASK_DATA_1_LSW HIGH BANK [47:32]</H1>
-<H1>MASK_DATA_1_MSW HIGH BANK [53:48]</H1>
-<H1>NOR CHIP SELECT</H1>
-<H1>DIR MODE BANK 0</H1>
-<H1>MASK_DATA_0_LSW HIGH BANK [15:0]</H1>
-<H1>OUTPUT ENABLE BANK 0</H1>
-</TABLE>
-<P>
-<H2><a name="ps7_post_config_1_0">ps7_post_config_1_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_UNLOCK">
-SLCR_UNLOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LVL_SHFTR_EN">
-LVL_SHFTR_EN
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000900</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Level Shifters Enable</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#FPGA_RST_CTRL">
-FPGA_RST_CTRL
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000240</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>RW</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA Software Reset Control</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#SLCR_LOCK">
-SLCR_LOCK
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_post_config_1_0">ps7_post_config_1_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>SLCR SETTINGS</H1>
-<H2><a name="SLCR_UNLOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_UNLOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_UNLOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000008</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>UNLOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_UNLOCK@0XF8000008</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>df0d</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Unlock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ENABLING LEVEL SHIFTER</H1>
-<H2><a name="LVL_SHFTR_EN">Register (<A href=#mod___slcr> slcr </A>)LVL_SHFTR_EN</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LVL_SHFTR_EN</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000900</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>USER_INP_ICT_EN_0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0].</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>USER_INP_ICT_EN_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0].</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LVL_SHFTR_EN@0XF8000900</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>f</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>f</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Level Shifters Enable</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>FPGA RESETS TO 0</H1>
-<H2><a name="FPGA_RST_CTRL">Register (<A href=#mod___slcr> slcr </A>)FPGA_RST_CTRL</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_RST_CTRL</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000240</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_3</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:25</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>fe000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Writes are ignored, read data is always zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_ACP_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>24:24</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_AXDS3_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>23:23</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_AXDS2_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>22:22</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_AXDS1_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>21:21</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_AXDS0_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>20:20</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_2</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>19:18</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c0000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Writes are ignored, read data is always zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FSSW1_FPGA_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>17:17</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>20000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FSSW0_FPGA_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>16:16</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>10000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved_1</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:14</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Writes are ignored, read data is always zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_FMSW1_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>13:13</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_FMSW0_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>12:12</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1000</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_DMA3_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>11:11</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>800</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_DMA2_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>10:10</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>400</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_DMA1_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>9:9</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>200</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA_DMA0_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>8:8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>100</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>reserved</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>7:4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>f0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Reserved. Writes are ignored, read data is always zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA3_OUT_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>3:3</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>8</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA2_OUT_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>2:2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>4</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA1_OUT_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>1:1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>2</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>FPGA0_OUT_RST</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>1</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>FPGA_RST_CTRL@0XF8000240</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>0</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>FPGA Software Reset Control</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>AFI REGISTERS</H1>
-<H1>AFI0 REGISTERS</H1>
-<H1>AFI1 REGISTERS</H1>
-<H1>AFI2 REGISTERS</H1>
-<H1>AFI3 REGISTERS</H1>
-<H1>LOCK IT BACK</H1>
-<H2><a name="SLCR_LOCK">Register (<A href=#mod___slcr> slcr </A>)SLCR_LOCK</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>SLCR_LOCK</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8000004</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LOCK_KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>15:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>SLCR_LOCK@0XF8000004</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>767b</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>SLCR Write Protection Lock</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-</TABLE>
-<P>
-<H2><a name="ps7_debug_1_0">ps7_debug_1_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LAR">
-LAR
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8898FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LAR">
-LAR
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8899FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<A href="#LAR">
-LAR
-</A>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8809FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>WO</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="ps7_debug_1_0">ps7_debug_1_0</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFC0FF>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFC0FF>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFC0FF>
-<B>Description</B>
-</TD>
-</TR>
-<H1>CROSS TRIGGER CONFIGURATIONS</H1>
-<H1>UNLOCKING CTI REGISTERS</H1>
-<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LAR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8898FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LAR@0XF8898FB0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LAR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8899FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LAR@0XF8899FB0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H2><a name="LAR">Register (<A href=#mod___slcr> slcr </A>)LAR</a></H2>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Register Name</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Address</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Width</B>
-</TD>
-<TD width=10% BGCOLOR=#FFFF00>
-<B>Type</B>
-</TD>
-<TD width=15% BGCOLOR=#FFFF00>
-<B>Reset Value</B>
-</TD>
-<TD width=35% BGCOLOR=#FFFF00>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>LAR</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0XF8809FB0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>32</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>rw</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>0x00000000</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>--</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Field Name</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Bits</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Mask</B>
-</TD>
-<TD width=10% BGCOLOR=#C0FFC0>
-<B>Value</B>
-</TD>
-<TD width=15% BGCOLOR=#C0FFC0>
-<B>Shifted Value</B>
-</TD>
-<TD width=35% BGCOLOR=#C0FFC0>
-<B>Description</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>KEY</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=15% BGCOLOR=#FBF5EF>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#FBF5EF>
-<B>Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.</B>
-</TD>
-</TR>
-<TR valign="top">
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>LAR@0XF8809FB0</B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>31:0</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B>ffffffff</B>
-</TD>
-<TD width=10% BGCOLOR=#C0C0C0>
-<B></B>
-</TD>
-<TD width=15% BGCOLOR=#C0C0C0>
-<B>c5acce55</B>
-</TD>
-<TD width=35% BGCOLOR=#C0C0C0>
-<B>Lock Access Register</B>
-</TD>
-</TR>
-</TABLE>
-<P>
-<H1>ENABLING CTI MODULES AND CHANNELS</H1>
-<H1>MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS</H1>
-</TABLE>
-<P>
-</body>
-</head>
-</body>
-</html>
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init.tcl b/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init.tcl
deleted file mode 100644
index f87627a1b..000000000
--- a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init.tcl
+++ /dev/null
@@ -1,862 +0,0 @@
-proc ps7_pll_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001772C0
- mask_write 0XF8000100 0x0007F000 0x0001A000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001DB2C0
- mask_write 0XF8000104 0x0007F000 0x00015000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x001F42C0
- mask_write 0XF8000108 0x0007F000 0x00014000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203401
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100801
- mask_write 0XF800014C 0x00003F31 0x00000501
- mask_write 0XF8000150 0x00003F33 0x00001401
- mask_write 0XF8000154 0x00003F33 0x00000A03
- mask_write 0XF8000168 0x00003F31 0x00000501
- mask_write 0XF8000170 0x03F03F30 0x00200500
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_3_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000080
- mask_write 0XF8006004 0x0007FFFF 0x0000107F
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x0004151A
- mask_write 0XF8006018 0xF7FFFFFF 0x44E354D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
- mask_write 0XF8006024 0x0FFFFFC3 0x00000000
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011674
- mask_write 0XF8006038 0x00000003 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000777
- mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
- mask_write 0XF8006048 0x0003F03F 0x0003C008
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x00010000 0x00000000
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00466111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0670C845
- mask_write 0XF80060AC 0x000001FF 0x000001FE
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x00000200 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFCF 0x40000001
- mask_write 0XF800611C 0x7FFFFFCF 0x40000001
- mask_write 0XF8006120 0x7FFFFFCF 0x40000001
- mask_write 0XF8006124 0x7FFFFFCF 0x40000001
- mask_write 0XF800612C 0x000FFFFF 0x00023C00
- mask_write 0XF8006130 0x000FFFFF 0x00022800
- mask_write 0XF8006134 0x000FFFFF 0x00022C00
- mask_write 0XF8006138 0x000FFFFF 0x00024800
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000077
- mask_write 0XF8006158 0x000FFFFF 0x0000007C
- mask_write 0XF800615C 0x000FFFFF 0x0000007C
- mask_write 0XF8006160 0x000FFFFF 0x00000075
- mask_write 0XF8006168 0x001FFFFF 0x000000E4
- mask_write 0XF800616C 0x001FFFFF 0x000000DF
- mask_write 0XF8006170 0x001FFFFF 0x000000E0
- mask_write 0XF8006174 0x001FFFFF 0x000000E7
- mask_write 0XF800617C 0x000FFFFF 0x000000B7
- mask_write 0XF8006180 0x000FFFFF 0x000000BC
- mask_write 0XF8006184 0x000FFFFF 0x000000BC
- mask_write 0XF8006188 0x000FFFFF 0x000000B5
- mask_write 0XF8006190 0x6FFFFEFE 0x00040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000703FF 0x000003FF
- mask_write 0XF800620C 0x000703FF 0x000003FF
- mask_write 0XF8006210 0x000703FF 0x000003FF
- mask_write 0XF8006214 0x000703FF 0x000003FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF5 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005125
- mask_write 0XF80062B4 0x0003FFFF 0x000012A6
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000081
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B00 0x00000071 0x00000001
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000672
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000674
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
- mask_write 0XF8000B6C 0x00007FFF 0x00000260
- mask_write 0XF8000B70 0x00000001 0x00000001
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FEFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00000702
- mask_write 0XF8000708 0x00003FFF 0x00000702
- mask_write 0XF800070C 0x00003FFF 0x00000702
- mask_write 0XF8000710 0x00003FFF 0x00000702
- mask_write 0XF8000714 0x00003FFF 0x00000702
- mask_write 0XF8000718 0x00003FFF 0x00000702
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000702
- mask_write 0XF8000724 0x00003FFF 0x00001600
- mask_write 0XF8000728 0x00003FFF 0x00001640
- mask_write 0XF800072C 0x00003FFF 0x00001640
- mask_write 0XF8000730 0x00003FFF 0x00001640
- mask_write 0XF8000734 0x00003FFF 0x00001640
- mask_write 0XF8000738 0x00003FFF 0x00001600
- mask_write 0XF800073C 0x00003FFF 0x00001600
- mask_write 0XF8000740 0x00003FFF 0x00002902
- mask_write 0XF8000744 0x00003FFF 0x00002902
- mask_write 0XF8000748 0x00003FFF 0x00002902
- mask_write 0XF800074C 0x00003FFF 0x00002902
- mask_write 0XF8000750 0x00003FFF 0x00002902
- mask_write 0XF8000754 0x00003FFF 0x00002902
- mask_write 0XF8000758 0x00003FFF 0x00000903
- mask_write 0XF800075C 0x00003FFF 0x00000903
- mask_write 0XF8000760 0x00003FFF 0x00000903
- mask_write 0XF8000764 0x00003FFF 0x00000903
- mask_write 0XF8000768 0x00003FFF 0x00000903
- mask_write 0XF800076C 0x00003FFF 0x00000903
- mask_write 0XF8000770 0x00003FFF 0x00000304
- mask_write 0XF8000774 0x00003FFF 0x00000305
- mask_write 0XF8000778 0x00003FFF 0x00000304
- mask_write 0XF800077C 0x00003FFF 0x00000305
- mask_write 0XF8000780 0x00003FFF 0x00000304
- mask_write 0XF8000784 0x00003FFF 0x00000304
- mask_write 0XF8000788 0x00003FFF 0x00000304
- mask_write 0XF800078C 0x00003FFF 0x00000304
- mask_write 0XF8000790 0x00003FFF 0x00000305
- mask_write 0XF8000794 0x00003FFF 0x00000304
- mask_write 0XF8000798 0x00003FFF 0x00000304
- mask_write 0XF800079C 0x00003FFF 0x00000304
- mask_write 0XF80007A0 0x00003FFF 0x00000380
- mask_write 0XF80007A4 0x00003FFF 0x00000380
- mask_write 0XF80007A8 0x00003FFF 0x00000380
- mask_write 0XF80007AC 0x00003FFF 0x00000380
- mask_write 0XF80007B0 0x00003FFF 0x00000380
- mask_write 0XF80007B4 0x00003FFF 0x00000380
- mask_write 0XF80007B8 0x00003FFF 0x00001200
- mask_write 0XF80007BC 0x00003F01 0x00000201
- mask_write 0XF80007C0 0x00003FFF 0x000002E0
- mask_write 0XF80007C4 0x00003FFF 0x000002E1
- mask_write 0XF80007C8 0x00003FFF 0x00000200
- mask_write 0XF80007CC 0x00003FFF 0x00000200
- mask_write 0XF80007D0 0x00003FFF 0x00000200
- mask_write 0XF80007D4 0x00003FFF 0x00000200
- mask_write 0XF8000830 0x003F003F 0x002F0037
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000180
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000180
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x000003FF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x000003FF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
- mask_write 0XE000A244 0x003FFFFF 0x00004000
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
- mask_write 0XE000A248 0x003FFFFF 0x00004000
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
- mask_delay 0XF8F00200 1
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
- mask_delay 0XF8F00200 1
- mask_delay 0XF8F00200 1
- mask_delay 0XF8F00200 1
- mask_delay 0XF8F00200 1
- mask_delay 0XF8F00200 1
-}
-proc ps7_post_config_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_3_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001772C0
- mask_write 0XF8000100 0x0007F000 0x0001A000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001DB2C0
- mask_write 0XF8000104 0x0007F000 0x00015000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x001F42C0
- mask_write 0XF8000108 0x0007F000 0x00014000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203401
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100801
- mask_write 0XF800014C 0x00003F31 0x00000501
- mask_write 0XF8000150 0x00003F33 0x00001401
- mask_write 0XF8000154 0x00003F33 0x00000A03
- mask_write 0XF8000168 0x00003F31 0x00000501
- mask_write 0XF8000170 0x03F03F30 0x00200500
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_2_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000080
- mask_write 0XF8006004 0x1FFFFFFF 0x0008107F
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x0004151A
- mask_write 0XF8006018 0xF7FFFFFF 0x44E354D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011674
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000777
- mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00466111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0670C845
- mask_write 0XF80060AC 0x000001FF 0x000001FE
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000001
- mask_write 0XF8006124 0x7FFFFFFF 0x40000001
- mask_write 0XF800612C 0x000FFFFF 0x00023C00
- mask_write 0XF8006130 0x000FFFFF 0x00022800
- mask_write 0XF8006134 0x000FFFFF 0x00022C00
- mask_write 0XF8006138 0x000FFFFF 0x00024800
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000077
- mask_write 0XF8006158 0x000FFFFF 0x0000007C
- mask_write 0XF800615C 0x000FFFFF 0x0000007C
- mask_write 0XF8006160 0x000FFFFF 0x00000075
- mask_write 0XF8006168 0x001FFFFF 0x000000E4
- mask_write 0XF800616C 0x001FFFFF 0x000000DF
- mask_write 0XF8006170 0x001FFFFF 0x000000E0
- mask_write 0XF8006174 0x001FFFFF 0x000000E7
- mask_write 0XF800617C 0x000FFFFF 0x000000B7
- mask_write 0XF8006180 0x000FFFFF 0x000000BC
- mask_write 0XF8006184 0x000FFFFF 0x000000BC
- mask_write 0XF8006188 0x000FFFFF 0x000000B5
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005125
- mask_write 0XF80062B4 0x0003FFFF 0x000012A6
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000081
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B00 0x00000303 0x00000001
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000672
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000674
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
- mask_write 0XF8000B6C 0x00007FFF 0x00000260
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00000702
- mask_write 0XF8000708 0x00003FFF 0x00000702
- mask_write 0XF800070C 0x00003FFF 0x00000702
- mask_write 0XF8000710 0x00003FFF 0x00000702
- mask_write 0XF8000714 0x00003FFF 0x00000702
- mask_write 0XF8000718 0x00003FFF 0x00000702
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000702
- mask_write 0XF8000724 0x00003FFF 0x00001600
- mask_write 0XF8000728 0x00003FFF 0x00001640
- mask_write 0XF800072C 0x00003FFF 0x00001640
- mask_write 0XF8000730 0x00003FFF 0x00001640
- mask_write 0XF8000734 0x00003FFF 0x00001640
- mask_write 0XF8000738 0x00003FFF 0x00001600
- mask_write 0XF800073C 0x00003FFF 0x00001600
- mask_write 0XF8000740 0x00003FFF 0x00002902
- mask_write 0XF8000744 0x00003FFF 0x00002902
- mask_write 0XF8000748 0x00003FFF 0x00002902
- mask_write 0XF800074C 0x00003FFF 0x00002902
- mask_write 0XF8000750 0x00003FFF 0x00002902
- mask_write 0XF8000754 0x00003FFF 0x00002902
- mask_write 0XF8000758 0x00003FFF 0x00000903
- mask_write 0XF800075C 0x00003FFF 0x00000903
- mask_write 0XF8000760 0x00003FFF 0x00000903
- mask_write 0XF8000764 0x00003FFF 0x00000903
- mask_write 0XF8000768 0x00003FFF 0x00000903
- mask_write 0XF800076C 0x00003FFF 0x00000903
- mask_write 0XF8000770 0x00003FFF 0x00000304
- mask_write 0XF8000774 0x00003FFF 0x00000305
- mask_write 0XF8000778 0x00003FFF 0x00000304
- mask_write 0XF800077C 0x00003FFF 0x00000305
- mask_write 0XF8000780 0x00003FFF 0x00000304
- mask_write 0XF8000784 0x00003FFF 0x00000304
- mask_write 0XF8000788 0x00003FFF 0x00000304
- mask_write 0XF800078C 0x00003FFF 0x00000304
- mask_write 0XF8000790 0x00003FFF 0x00000305
- mask_write 0XF8000794 0x00003FFF 0x00000304
- mask_write 0XF8000798 0x00003FFF 0x00000304
- mask_write 0XF800079C 0x00003FFF 0x00000304
- mask_write 0XF80007A0 0x00003FFF 0x00000380
- mask_write 0XF80007A4 0x00003FFF 0x00000380
- mask_write 0XF80007A8 0x00003FFF 0x00000380
- mask_write 0XF80007AC 0x00003FFF 0x00000380
- mask_write 0XF80007B0 0x00003FFF 0x00000380
- mask_write 0XF80007B4 0x00003FFF 0x00000380
- mask_write 0XF80007B8 0x00003FFF 0x00001200
- mask_write 0XF80007BC 0x00003F01 0x00000201
- mask_write 0XF80007C0 0x00003FFF 0x000002E0
- mask_write 0XF80007C4 0x00003FFF 0x000002E1
- mask_write 0XF80007C8 0x00003FFF 0x00000200
- mask_write 0XF80007CC 0x00003FFF 0x00000200
- mask_write 0XF80007D0 0x00003FFF 0x00000200
- mask_write 0XF80007D4 0x00003FFF 0x00000200
- mask_write 0XF8000830 0x003F003F 0x002F0037
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000180
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000180
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
- mask_write 0XE000A244 0x003FFFFF 0x00004000
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
- mask_write 0XE000A248 0x003FFFFF 0x00004000
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
- mask_delay 0XF8F00200 1
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
- mask_delay 0XF8F00200 1
- mask_delay 0XF8F00200 1
- mask_delay 0XF8F00200 1
- mask_delay 0XF8F00200 1
- mask_delay 0XF8F00200 1
-}
-proc ps7_post_config_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_2_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001772C0
- mask_write 0XF8000100 0x0007F000 0x0001A000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001DB2C0
- mask_write 0XF8000104 0x0007F000 0x00015000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x001F42C0
- mask_write 0XF8000108 0x0007F000 0x00014000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203401
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100801
- mask_write 0XF800014C 0x00003F31 0x00000501
- mask_write 0XF8000150 0x00003F33 0x00001401
- mask_write 0XF8000154 0x00003F33 0x00000A03
- mask_write 0XF8000168 0x00003F31 0x00000501
- mask_write 0XF8000170 0x03F03F30 0x00200500
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_1_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000080
- mask_write 0XF8006004 0x1FFFFFFF 0x0008107F
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x0004151A
- mask_write 0XF8006018 0xF7FFFFFF 0x44E354D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011674
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000777
- mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0670C845
- mask_write 0XF80060AC 0x000001FF 0x000001FE
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000001
- mask_write 0XF8006124 0x7FFFFFFF 0x40000001
- mask_write 0XF800612C 0x000FFFFF 0x00023C00
- mask_write 0XF8006130 0x000FFFFF 0x00022800
- mask_write 0XF8006134 0x000FFFFF 0x00022C00
- mask_write 0XF8006138 0x000FFFFF 0x00024800
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000077
- mask_write 0XF8006158 0x000FFFFF 0x0000007C
- mask_write 0XF800615C 0x000FFFFF 0x0000007C
- mask_write 0XF8006160 0x000FFFFF 0x00000075
- mask_write 0XF8006168 0x001FFFFF 0x000000E4
- mask_write 0XF800616C 0x001FFFFF 0x000000DF
- mask_write 0XF8006170 0x001FFFFF 0x000000E0
- mask_write 0XF8006174 0x001FFFFF 0x000000E7
- mask_write 0XF800617C 0x000FFFFF 0x000000B7
- mask_write 0XF8006180 0x000FFFFF 0x000000BC
- mask_write 0XF8006184 0x000FFFFF 0x000000BC
- mask_write 0XF8006188 0x000FFFFF 0x000000B5
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005125
- mask_write 0XF80062B4 0x0003FFFF 0x000012A6
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000081
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B00 0x00000303 0x00000001
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000672
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000674
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
- mask_write 0XF8000B6C 0x000073FF 0x00000260
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00000702
- mask_write 0XF8000708 0x00003FFF 0x00000702
- mask_write 0XF800070C 0x00003FFF 0x00000702
- mask_write 0XF8000710 0x00003FFF 0x00000702
- mask_write 0XF8000714 0x00003FFF 0x00000702
- mask_write 0XF8000718 0x00003FFF 0x00000702
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000702
- mask_write 0XF8000724 0x00003FFF 0x00001600
- mask_write 0XF8000728 0x00003FFF 0x00001640
- mask_write 0XF800072C 0x00003FFF 0x00001640
- mask_write 0XF8000730 0x00003FFF 0x00001640
- mask_write 0XF8000734 0x00003FFF 0x00001640
- mask_write 0XF8000738 0x00003FFF 0x00001600
- mask_write 0XF800073C 0x00003FFF 0x00001600
- mask_write 0XF8000740 0x00003FFF 0x00002902
- mask_write 0XF8000744 0x00003FFF 0x00002902
- mask_write 0XF8000748 0x00003FFF 0x00002902
- mask_write 0XF800074C 0x00003FFF 0x00002902
- mask_write 0XF8000750 0x00003FFF 0x00002902
- mask_write 0XF8000754 0x00003FFF 0x00002902
- mask_write 0XF8000758 0x00003FFF 0x00000903
- mask_write 0XF800075C 0x00003FFF 0x00000903
- mask_write 0XF8000760 0x00003FFF 0x00000903
- mask_write 0XF8000764 0x00003FFF 0x00000903
- mask_write 0XF8000768 0x00003FFF 0x00000903
- mask_write 0XF800076C 0x00003FFF 0x00000903
- mask_write 0XF8000770 0x00003FFF 0x00000304
- mask_write 0XF8000774 0x00003FFF 0x00000305
- mask_write 0XF8000778 0x00003FFF 0x00000304
- mask_write 0XF800077C 0x00003FFF 0x00000305
- mask_write 0XF8000780 0x00003FFF 0x00000304
- mask_write 0XF8000784 0x00003FFF 0x00000304
- mask_write 0XF8000788 0x00003FFF 0x00000304
- mask_write 0XF800078C 0x00003FFF 0x00000304
- mask_write 0XF8000790 0x00003FFF 0x00000305
- mask_write 0XF8000794 0x00003FFF 0x00000304
- mask_write 0XF8000798 0x00003FFF 0x00000304
- mask_write 0XF800079C 0x00003FFF 0x00000304
- mask_write 0XF80007A0 0x00003FFF 0x00000380
- mask_write 0XF80007A4 0x00003FFF 0x00000380
- mask_write 0XF80007A8 0x00003FFF 0x00000380
- mask_write 0XF80007AC 0x00003FFF 0x00000380
- mask_write 0XF80007B0 0x00003FFF 0x00000380
- mask_write 0XF80007B4 0x00003FFF 0x00000380
- mask_write 0XF80007B8 0x00003FFF 0x00001200
- mask_write 0XF80007BC 0x00003F01 0x00000201
- mask_write 0XF80007C0 0x00003FFF 0x000002E0
- mask_write 0XF80007C4 0x00003FFF 0x000002E1
- mask_write 0XF80007C8 0x00003FFF 0x00000200
- mask_write 0XF80007CC 0x00003FFF 0x00000200
- mask_write 0XF80007D0 0x00003FFF 0x00000200
- mask_write 0XF80007D4 0x00003FFF 0x00000200
- mask_write 0XF8000830 0x003F003F 0x002F0037
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000180
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000180
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
- mask_write 0XE000A244 0x003FFFFF 0x00004000
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
- mask_write 0XE000A248 0x003FFFFF 0x00004000
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
- mask_delay 0XF8F00200 1
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
- mask_delay 0XF8F00200 1
- mask_delay 0XF8F00200 1
- mask_delay 0XF8F00200 1
- mask_delay 0XF8F00200 1
- mask_delay 0XF8F00200 1
-}
-proc ps7_post_config_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_1_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-set PCW_SILICON_VER_1_0 "0x0"
-set PCW_SILICON_VER_2_0 "0x1"
-set PCW_SILICON_VER_3_0 "0x2"
-set APU_FREQ 650000000
-
-
-
-proc mask_poll { addr mask } {
- set count 1
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- while { $maskedval == 0 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- set count [ expr { $count + 1 } ]
- if { $count == 100000000 } {
- puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
- break
- }
- }
-}
-
-
-
-proc mask_delay { addr val } {
- set delay [ get_number_of_cycles_for_delay $val ]
- perf_reset_and_start_timer
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- while { $maskedval == 1 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- }
- perf_reset_clock
-}
-
-proc ps_version { } {
- set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
- set mask_sil_ver "0x[expr {$si_ver >> 28}]"
- return $mask_sil_ver;
-}
-
-proc ps7_post_config {} {
- set saved_mode [configparams force-mem-accesses]
- configparams force-mem-accesses 1
-
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_post_config_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_post_config_2_0
- } else {
- ps7_post_config_3_0
- }
- configparams force-mem-accesses $saved_mode
-}
-
-proc ps7_debug {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_debug_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_debug_2_0
- } else {
- ps7_debug_3_0
- }
-}
-proc ps7_init {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_mio_init_data_1_0
- ps7_pll_init_data_1_0
- ps7_clock_init_data_1_0
- ps7_ddr_init_data_1_0
- ps7_peripherals_init_data_1_0
- #puts "PCW Silicon Version : 1.0"
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_mio_init_data_2_0
- ps7_pll_init_data_2_0
- ps7_clock_init_data_2_0
- ps7_ddr_init_data_2_0
- ps7_peripherals_init_data_2_0
- #puts "PCW Silicon Version : 2.0"
- } else {
- ps7_mio_init_data_3_0
- ps7_pll_init_data_3_0
- ps7_clock_init_data_3_0
- ps7_ddr_init_data_3_0
- ps7_peripherals_init_data_3_0
- #puts "PCW Silicon Version : 3.0"
- }
-}
-
-
-# For delay calculation using global timer
-
-# start timer
- proc perf_start_clock { } {
-
- #writing SCU_GLOBAL_TIMER_CONTROL register
-
- mask_write 0xF8F00208 0x00000109 0x00000009
-}
-
-# stop timer and reset timer count regs
- proc perf_reset_clock { } {
- perf_disable_clock
- mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
- mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
-}
-
-# Compute mask for given delay in miliseconds
-proc get_number_of_cycles_for_delay { delay } {
-
- # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- variable APU_FREQ
- return [ expr ($delay * $APU_FREQ /(2 * 1000))]
-}
-
-
-# stop timer
-proc perf_disable_clock {} {
- mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
-}
-
-proc perf_reset_and_start_timer {} {
- perf_reset_clock
- perf_start_clock
-}
-
-
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init_gpl.c b/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init_gpl.c
deleted file mode 100644
index 76ebc528f..000000000
--- a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init_gpl.c
+++ /dev/null
@@ -1,13116 +0,0 @@
-/******************************************************************************
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
-*
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init_gpl.c
-*
-* This file is automatically generated
-*
-*****************************************************************************/
-
-#include "ps7_init_gpl.h"
-
-unsigned long ps7_pll_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x177
- // .. .. ==> 0XF8000110[21:12] = 0x00000177U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1a
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1db
- // .. .. ==> 0XF8000114[21:12] = 0x000001DBU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x15
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000118[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x34
- // .. ==> 0XF8000128[13:8] = 0x00000034U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003400U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000154[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xa
- // .. ==> 0XF8000154[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
- // .. .. START: TRACE CLOCK
- // .. .. FINISH: TRACE CLOCK
- // .. .. CLKACT = 0x1
- // .. .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR = 0x5
- // .. .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // .. ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR0 = 0x5
- // .. .. ==> 0XF8000170[13:8] = 0x00000005U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // .. .. DIVISOR1 = 0x2
- // .. .. ==> 0XF8000170[25:20] = 0x00000002U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
- // .. .. CLK_621_TRUE = 0x1
- // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. .. DMA_CPU_2XCLKACT = 0x1
- // .. .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. USB0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. USB1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. .. GEM0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. .. GEM1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. SDI0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. .. SDI1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. SPI0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. SPI1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. CAN0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. CAN1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. I2C0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. .. I2C1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. .. UART0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. .. UART1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. GPIO_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. .. LQSPI_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. .. SMC_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_3_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f
- // .. .. ==> 0XF8006004[11:0] = 0x0000007FU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU
- // .. .. reserved_reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x0000107FU),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1a
- // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
- // .. .. reg_ddrc_t_rfc_min = 0x54
- // .. .. ==> 0XF8006014[13:6] = 0x00000054U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x15
- // .. .. ==> 0XF8006018[15:10] = 0x00000015U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U
- // .. .. reg_ddrc_t_ras_max = 0x23
- // .. .. ==> 0XF8006018[21:16] = 0x00000023U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U
- // .. .. reg_ddrc_t_ras_min = 0x13
- // .. .. ==> 0XF8006018[26:22] = 0x00000013U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x6
- // .. .. ==> 0XF8006020[7:5] = 0x00000006U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x167
- // .. .. ==> 0XF8006034[13:4] = 0x00000167U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011674U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x6
- // .. .. ==> 0XF8006078[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_t_cksrx = 0x6
- // .. .. ==> 0XF8006078[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xc845
- // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U
- // .. .. dram_rstn_x1024 = 0x67
- // .. .. ==> 0XF80060A8[27:20] = 0x00000067U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8f
- // .. .. ==> 0XF800612C[19:10] = 0x0000008FU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8a
- // .. .. ==> 0XF8006130[19:10] = 0x0000008AU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8b
- // .. .. ==> 0XF8006134[19:10] = 0x0000008BU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x92
- // .. .. ==> 0XF8006138[19:10] = 0x00000092U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. .. ==> 0XF8006154[9:0] = 0x00000077U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. .. ==> 0XF8006158[9:0] = 0x0000007CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. .. ==> 0XF800615C[9:0] = 0x0000007CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x75
- // .. .. ==> 0XF8006160[9:0] = 0x00000075U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe4
- // .. .. ==> 0XF8006168[10:0] = 0x000000E4U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xdf
- // .. .. ==> 0XF800616C[10:0] = 0x000000DFU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe0
- // .. .. ==> 0XF8006170[10:0] = 0x000000E0U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe7
- // .. .. ==> 0XF8006174[10:0] = 0x000000E7U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. .. ==> 0XF8006180[9:0] = 0x000000BCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. .. ==> 0XF8006184[9:0] = 0x000000BCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb5
- // .. .. ==> 0XF8006188[9:0] = 0x000000B5U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U),
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa6
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A6U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B00[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. reserved_SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x0
- // .. ==> 0XF8000B6C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B6C[4:1] = 0x00000000U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
- // .. VREF_EXT_EN = 0x3
- // .. ==> 0XF8000B6C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. reserved_VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. reserved_REFIO_TEST = 0x0
- // .. ==> 0XF8000B6C[11:10] = 0x00000000U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
- // .. reserved_REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reserved_VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reserved_VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reserved_VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reserved_VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reserved_VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reserved_INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reserved_TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reserved_TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reserved_TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. reserved_TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reserved_INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000704[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000708[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800070C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000710[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000714[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000718[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000720[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000728[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF800072C[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000730[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000734[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800073C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000740[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000744[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000748[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800074C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000750[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000754[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000758[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800075C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000760[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000764[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000768[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800076C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000770[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000774[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000778[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800077C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000780[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000784[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000788[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800078C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000790[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000794[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000798[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800079C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A8[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007AC[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007B8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007BC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007C8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007CC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007D0[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007D4[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000200U),
- // .. SDIO0_WP_SEL = 55
- // .. ==> 0XF8000830[5:0] = 0x00000037U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000037U
- // .. SDIO0_CD_SEL = 47
- // .. ==> 0XF8000830[21:16] = 0x0000002FU
- // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0001018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
- // .. BDIV = 0x6
- // .. ==> 0XE0000034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0000018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0000000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0000000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0000000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0000000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0000000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0000000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0000000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0000000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0000000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
- // .. CHMODE = 0x0
- // .. ==> 0XE0000004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0000004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0000004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0000004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0000004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. DIRECTION_1 = 0x4000
- // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. OP_ENABLE_1 = 0x4000
- // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x0
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_LVL_INP_EN_0 = 1
- // .. ==> 0XF8000900[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. USER_LVL_OUT_EN_0 = 1
- // .. ==> 0XF8000900[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USER_LVL_INP_EN_1 = 1
- // .. ==> 0XF8000900[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. USER_LVL_OUT_EN_1 = 1
- // .. ==> 0XF8000900[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. reserved_FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. reserved_FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reserved_FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reserved_FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reserved_FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. reserved_FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. .. START: AFI2 SECURE REGISTER
- // .. .. FINISH: AFI2 SECURE REGISTER
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x177
- // .. .. ==> 0XF8000110[21:12] = 0x00000177U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1a
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1db
- // .. .. ==> 0XF8000114[21:12] = 0x000001DBU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x15
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000118[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x34
- // .. ==> 0XF8000128[13:8] = 0x00000034U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003400U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000154[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xa
- // .. ==> 0XF8000154[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
- // .. .. START: TRACE CLOCK
- // .. .. FINISH: TRACE CLOCK
- // .. .. CLKACT = 0x1
- // .. .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR = 0x5
- // .. .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // .. ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR0 = 0x5
- // .. .. ==> 0XF8000170[13:8] = 0x00000005U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // .. .. DIVISOR1 = 0x2
- // .. .. ==> 0XF8000170[25:20] = 0x00000002U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
- // .. .. CLK_621_TRUE = 0x1
- // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. .. DMA_CPU_2XCLKACT = 0x1
- // .. .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. USB0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. USB1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. .. GEM0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. .. GEM1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. SDI0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. .. SDI1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. SPI0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. SPI1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. CAN0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. CAN1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. I2C0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. .. I2C1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. .. UART0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. .. UART1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. GPIO_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. .. LQSPI_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. .. SMC_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_2_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f
- // .. .. ==> 0XF8006004[11:0] = 0x0000007FU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x0008107FU),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1a
- // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
- // .. .. reg_ddrc_t_rfc_min = 0x54
- // .. .. ==> 0XF8006014[13:6] = 0x00000054U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x15
- // .. .. ==> 0XF8006018[15:10] = 0x00000015U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U
- // .. .. reg_ddrc_t_ras_max = 0x23
- // .. .. ==> 0XF8006018[21:16] = 0x00000023U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U
- // .. .. reg_ddrc_t_ras_min = 0x13
- // .. .. ==> 0XF8006018[26:22] = 0x00000013U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x6
- // .. .. ==> 0XF8006020[7:5] = 0x00000006U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x167
- // .. .. ==> 0XF8006034[13:4] = 0x00000167U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011674U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x6
- // .. .. ==> 0XF8006078[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_t_cksrx = 0x6
- // .. .. ==> 0XF8006078[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xc845
- // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U
- // .. .. dram_rstn_x1024 = 0x67
- // .. .. ==> 0XF80060A8[27:20] = 0x00000067U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8f
- // .. .. ==> 0XF800612C[19:10] = 0x0000008FU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8a
- // .. .. ==> 0XF8006130[19:10] = 0x0000008AU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8b
- // .. .. ==> 0XF8006134[19:10] = 0x0000008BU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x92
- // .. .. ==> 0XF8006138[19:10] = 0x00000092U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. .. ==> 0XF8006154[9:0] = 0x00000077U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. .. ==> 0XF8006158[9:0] = 0x0000007CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. .. ==> 0XF800615C[9:0] = 0x0000007CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x75
- // .. .. ==> 0XF8006160[9:0] = 0x00000075U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe4
- // .. .. ==> 0XF8006168[10:0] = 0x000000E4U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xdf
- // .. .. ==> 0XF800616C[10:0] = 0x000000DFU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe0
- // .. .. ==> 0XF8006170[10:0] = 0x000000E0U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe7
- // .. .. ==> 0XF8006174[10:0] = 0x000000E7U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. .. ==> 0XF8006180[9:0] = 0x000000BCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. .. ==> 0XF8006184[9:0] = 0x000000BCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb5
- // .. .. ==> 0XF8006188[9:0] = 0x000000B5U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U),
- // .. .. reg_phy_loopback = 0x0
- // .. .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_use_rank0_delays = 0x1
- // .. .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_phy_int_lpbk = 0x0
- // .. .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_per_bank_refresh = 0x0
- // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa6
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A6U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. CLK_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. SRSTN_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x0
- // .. ==> 0XF8000B6C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B6C[4:1] = 0x00000000U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
- // .. VREF_EXT_EN = 0x3
- // .. ==> 0XF8000B6C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_TEST = 0x0
- // .. ==> 0XF8000B6C[11:10] = 0x00000000U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000704[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000708[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800070C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000710[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000714[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000718[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000720[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000728[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF800072C[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000730[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000734[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800073C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000740[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000744[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000748[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800074C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000750[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000754[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000758[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800075C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000760[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000764[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000768[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800076C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000770[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000774[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000778[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800077C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000780[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000784[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000788[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800078C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000790[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000794[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000798[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800079C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A8[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007AC[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007B8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007BC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007C8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007CC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007D0[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007D4[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000200U),
- // .. SDIO0_WP_SEL = 55
- // .. ==> 0XF8000830[5:0] = 0x00000037U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000037U
- // .. SDIO0_CD_SEL = 47
- // .. ==> 0XF8000830[21:16] = 0x0000002FU
- // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0001018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. BDIV = 0x6
- // .. ==> 0XE0000034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0000018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0000000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0000000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0000000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0000000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0000000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0000000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0000000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0000000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0000000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0000004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0000004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0000004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0000004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0000004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0000004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0000004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. DIRECTION_1 = 0x4000
- // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. OP_ENABLE_1 = 0x4000
- // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x0
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x177
- // .. .. ==> 0XF8000110[21:12] = 0x00000177U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1a
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1db
- // .. .. ==> 0XF8000114[21:12] = 0x000001DBU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x15
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000118[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x34
- // .. ==> 0XF8000128[13:8] = 0x00000034U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003400U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000154[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xa
- // .. ==> 0XF8000154[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
- // .. .. START: TRACE CLOCK
- // .. .. FINISH: TRACE CLOCK
- // .. .. CLKACT = 0x1
- // .. .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR = 0x5
- // .. .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // .. ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR0 = 0x5
- // .. .. ==> 0XF8000170[13:8] = 0x00000005U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // .. .. DIVISOR1 = 0x2
- // .. .. ==> 0XF8000170[25:20] = 0x00000002U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
- // .. .. CLK_621_TRUE = 0x1
- // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. .. DMA_CPU_2XCLKACT = 0x1
- // .. .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. USB0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. USB1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. .. GEM0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. .. GEM1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. SDI0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. .. SDI1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. SPI0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. SPI1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. CAN0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. CAN1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. I2C0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. .. I2C1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. .. UART0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. .. UART1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. GPIO_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. .. LQSPI_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. .. SMC_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_1_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f
- // .. .. ==> 0XF8006004[11:0] = 0x0000007FU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x0008107FU),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1a
- // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
- // .. .. reg_ddrc_t_rfc_min = 0x54
- // .. .. ==> 0XF8006014[13:6] = 0x00000054U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x15
- // .. .. ==> 0XF8006018[15:10] = 0x00000015U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U
- // .. .. reg_ddrc_t_ras_max = 0x23
- // .. .. ==> 0XF8006018[21:16] = 0x00000023U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U
- // .. .. reg_ddrc_t_ras_min = 0x13
- // .. .. ==> 0XF8006018[26:22] = 0x00000013U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x6
- // .. .. ==> 0XF8006020[7:5] = 0x00000006U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x167
- // .. .. ==> 0XF8006034[13:4] = 0x00000167U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011674U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xc845
- // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U
- // .. .. dram_rstn_x1024 = 0x67
- // .. .. ==> 0XF80060A8[27:20] = 0x00000067U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8f
- // .. .. ==> 0XF800612C[19:10] = 0x0000008FU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8a
- // .. .. ==> 0XF8006130[19:10] = 0x0000008AU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8b
- // .. .. ==> 0XF8006134[19:10] = 0x0000008BU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x92
- // .. .. ==> 0XF8006138[19:10] = 0x00000092U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. .. ==> 0XF8006154[9:0] = 0x00000077U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. .. ==> 0XF8006158[9:0] = 0x0000007CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. .. ==> 0XF800615C[9:0] = 0x0000007CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x75
- // .. .. ==> 0XF8006160[9:0] = 0x00000075U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe4
- // .. .. ==> 0XF8006168[10:0] = 0x000000E4U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xdf
- // .. .. ==> 0XF800616C[10:0] = 0x000000DFU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe0
- // .. .. ==> 0XF8006170[10:0] = 0x000000E0U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe7
- // .. .. ==> 0XF8006174[10:0] = 0x000000E7U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. .. ==> 0XF8006180[9:0] = 0x000000BCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. .. ==> 0XF8006184[9:0] = 0x000000BCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb5
- // .. .. ==> 0XF8006188[9:0] = 0x000000B5U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U),
- // .. .. reg_phy_loopback = 0x0
- // .. .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_use_rank0_delays = 0x1
- // .. .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_phy_int_lpbk = 0x0
- // .. .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_per_bank_refresh = 0x0
- // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa6
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A6U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. CLK_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. SRSTN_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x0
- // .. ==> 0XF8000B6C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B6C[4:1] = 0x00000000U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
- // .. VREF_EXT_EN = 0x3
- // .. ==> 0XF8000B6C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000704[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000708[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800070C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000710[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000714[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000718[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000720[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000728[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF800072C[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000730[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000734[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800073C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000740[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000744[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000748[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800074C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000750[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000754[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000758[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800075C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000760[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000764[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000768[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800076C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000770[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000774[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000778[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800077C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000780[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000784[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000788[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800078C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000790[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000794[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000798[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800079C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A8[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007AC[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007B8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007BC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007C8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007CC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007D0[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007D4[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000200U),
- // .. SDIO0_WP_SEL = 55
- // .. ==> 0XF8000830[5:0] = 0x00000037U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000037U
- // .. SDIO0_CD_SEL = 47
- // .. ==> 0XF8000830[21:16] = 0x0000002FU
- // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0001018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. BDIV = 0x6
- // .. ==> 0XE0000034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0000018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0000000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0000000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0000000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0000000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0000000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0000000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0000000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0000000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0000000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0000004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0000004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0000004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0000004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0000004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0000004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0000004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. DIRECTION_1 = 0x4000
- // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. OP_ENABLE_1 = 0x4000
- // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x0
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-
-#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
-
-unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
-unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
-unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
-unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-
-int
-ps7_post_config()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_post_config_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_post_config_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_post_config_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-
-int
-ps7_init()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret;
- //int pcw_ver = 0;
-
- if (si_ver == PCW_SILICON_VERSION_1) {
- ps7_mio_init_data = ps7_mio_init_data_1_0;
- ps7_pll_init_data = ps7_pll_init_data_1_0;
- ps7_clock_init_data = ps7_clock_init_data_1_0;
- ps7_ddr_init_data = ps7_ddr_init_data_1_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
- //pcw_ver = 1;
-
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ps7_mio_init_data = ps7_mio_init_data_2_0;
- ps7_pll_init_data = ps7_pll_init_data_2_0;
- ps7_clock_init_data = ps7_clock_init_data_2_0;
- ps7_ddr_init_data = ps7_ddr_init_data_2_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
- //pcw_ver = 2;
-
- } else {
- ps7_mio_init_data = ps7_mio_init_data_3_0;
- ps7_pll_init_data = ps7_pll_init_data_3_0;
- ps7_clock_init_data = ps7_clock_init_data_3_0;
- ps7_ddr_init_data = ps7_ddr_init_data_3_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
- //pcw_ver = 3;
- }
-
- // MIO init
- ret = ps7_config (ps7_mio_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // PLL init
- ret = ps7_config (ps7_pll_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // Clock init
- ret = ps7_config (ps7_clock_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // DDR init
- ret = ps7_config (ps7_ddr_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
-
-
- // Peripherals init
- ret = ps7_config (ps7_peripherals_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
- //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
- return PS7_INIT_SUCCESS;
-}
-
-
-
-
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
-
-
-
-
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init_gpl.h b/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init_gpl.h
deleted file mode 100644
index b88f82a5f..000000000
--- a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/ps7_init_gpl.h
+++ /dev/null
@@ -1,137 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy of this
-* software and associated documentation files (the "Software"), to deal in the Software
-* without restriction, including without limitation the rights to use, copy, modify, merge,
-* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
-* persons to whom the Software is furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in all copies or
-* substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
-* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or
-* otherwise to promote the sale, use or other dealings in this Software without prior written
-* authorization from Xilinx.
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 650000000
-#define DDR_FREQ 525000000
-#define DCI_FREQ 10096154
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 100000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 108333336
-#define WDT_FREQ 108333336
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 10000000
-#define FPGA2_FREQ 10000000
-#define FPGA3_FREQ 10000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/quad_wrapper.bit b/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/quad_wrapper.bit
deleted file mode 100644
index d437dcc33858ee864f6f31e178c1b41322f7a8c6..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001
literal 2083848
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diff --git a/quad/xsdk_workspace_vivado/real_quad/.cproject b/quad/xsdk_workspace_vivado/real_quad/.cproject
index c758d82d8..cb687f859 100644
--- a/quad/xsdk_workspace_vivado/real_quad/.cproject
+++ b/quad/xsdk_workspace_vivado/real_quad/.cproject
@@ -1,168 +1,150 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.arm.exe.debug.980189137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+ <cconfiguration id="xilinx.gnu.armv7.exe.debug.1245217687">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.armv7.exe.debug.1245217687" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
- <extension id="com.xilinx.sdk.managedbuilder.XELF.arm" point="org.eclipse.cdt.core.BinaryParser"/>
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+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
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</extensions>
</storageModule>
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+ <tool id="xilinx.gnu.armv7.toolchain.archiver.2045231509" name="ARM v7 archiver" superClass="xilinx.gnu.armv7.toolchain.archiver"/>
+ <tool id="xilinx.gnu.armv7.c.toolchain.linker.release.1233504244" name="ARM v7 gcc linker" superClass="xilinx.gnu.armv7.c.toolchain.linker.release">
+ <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1007503113" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/lib"/>
</option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.1169214283" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
+ <option id="xilinx.gnu.linker.inferred.swplatform.flags.1633933097" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
</option>
- <option id="xilinx.gnu.c.linker.option.lscript.1266246445" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
- <option id="xilinx.gnu.c.link.option.libs.962400757" name="Libraries (-l)" superClass="xilinx.gnu.c.link.option.libs" valueType="libs">
- <listOptionValue builtIn="false" value="m"/>
- </option>
- <inputType id="xilinx.gnu.linker.input.1933167678" superClass="xilinx.gnu.linker.input">
+ <option id="xilinx.gnu.c.linker.option.lscript.1391503865" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
+ <option id="xilinx.gnu.c.link.option.ldflags.1032159198" name="Linker Flags" superClass="xilinx.gnu.c.link.option.ldflags" value=" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec" valueType="string"/>
+ <inputType id="xilinx.gnu.linker.input.2000592538" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
- <inputType id="xilinx.gnu.linker.input.lscript.574206172" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
+ <inputType id="xilinx.gnu.linker.input.lscript.619596326" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
</tool>
- <tool id="xilinx.gnu.arm.cxx.toolchain.linker.release.1512126497" name="ARM g++ linker" superClass="xilinx.gnu.arm.cxx.toolchain.linker.release">
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1491656562" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
+ <tool id="xilinx.gnu.armv7.cxx.toolchain.linker.release.906108567" name="ARM v7 g++ linker" superClass="xilinx.gnu.armv7.cxx.toolchain.linker.release">
+ <option id="xilinx.gnu.linker.inferred.swplatform.lpath.359010680" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/lib"/>
</option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.1353247076" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
+ <option id="xilinx.gnu.linker.inferred.swplatform.flags.1749622312" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
</option>
- <option id="xilinx.gnu.c.linker.option.lscript.486002186" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
+ <option id="xilinx.gnu.c.linker.option.lscript.1678598473" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
</tool>
- <tool id="xilinx.gnu.arm.size.release.362029751" name="ARM Print Size" superClass="xilinx.gnu.arm.size.release"/>
+ <tool id="xilinx.gnu.armv7.size.release.1171671789" name="ARM v7 Print Size" superClass="xilinx.gnu.armv7.size.release"/>
</toolChain>
</folderInfo>
- <sourceEntries>
- <entry excluding="gen_diagram|test" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
- </sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
@@ -170,33 +152,29 @@
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <project id="modular_quad_pid.xilinx.gnu.arm.exe.832182557" name="Xilinx ARM Executable" projectType="xilinx.gnu.arm.exe"/>
- </storageModule>
- <storageModule moduleId="refreshScope" versionNumber="2">
- <configuration configurationName="Debug">
- <resource resourceType="PROJECT" workspacePath="/modular_quad_pid"/>
- </configuration>
- <configuration configurationName="Release">
- <resource resourceType="PROJECT" workspacePath="/modular_quad_pid"/>
- </configuration>
+ <project id="real_quad.xilinx.gnu.armv7.exe.673619442" name="Xilinx ARM v7 Executable" projectType="xilinx.gnu.armv7.exe"/>
</storageModule>
- <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.debug.980189137;xilinx.gnu.arm.exe.debug.980189137.">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
+ <scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.debug.1245217687;xilinx.gnu.armv7.exe.debug.1245217687.;xilinx.gnu.armv7.c.toolchain.compiler.debug.537645504;xilinx.gnu.armv7.c.compiler.input.276088888">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.release.255973624;xilinx.gnu.arm.exe.release.255973624.;xilinx.gnu.arm.c.toolchain.compiler.release.85270120;xilinx.gnu.arm.c.compiler.input.846429887">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
+ <scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.release.5476642;xilinx.gnu.armv7.exe.release.5476642.;xilinx.gnu.armv7.c.toolchain.compiler.release.1774347966;xilinx.gnu.armv7.c.compiler.input.1905976603">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.debug.980189137">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
+ <scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.release.5476642;xilinx.gnu.armv7.exe.release.5476642.">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.release.255973624;xilinx.gnu.arm.exe.release.255973624.">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
- </scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.debug.980189137;xilinx.gnu.arm.exe.debug.980189137.;xilinx.gnu.arm.c.toolchain.compiler.debug.177835003;xilinx.gnu.arm.c.compiler.input.909725989">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
+ <scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.debug.1245217687;xilinx.gnu.armv7.exe.debug.1245217687.">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
</storageModule>
+ <storageModule moduleId="refreshScope" versionNumber="2">
+ <configuration configurationName="Debug">
+ <resource resourceType="PROJECT" workspacePath="/real_quad"/>
+ </configuration>
+ <configuration configurationName="Release">
+ <resource resourceType="PROJECT" workspacePath="/real_quad"/>
+ </configuration>
+ </storageModule>
</cproject>
diff --git a/quad/xsdk_workspace_vivado/real_quad/.gitignore b/quad/xsdk_workspace_vivado/real_quad/.gitignore
index 8274dfc9f..3df573fe6 100644
--- a/quad/xsdk_workspace_vivado/real_quad/.gitignore
+++ b/quad/xsdk_workspace_vivado/real_quad/.gitignore
@@ -1,7 +1 @@
-*.o
-*.d
-*.elf
-*.size
-bootimage/
-Debug/
-Release/
\ No newline at end of file
+/Debug/
diff --git a/quad/xsdk_workspace_vivado/real_quad/.project b/quad/xsdk_workspace_vivado/real_quad/.project
index 46c57bad4..e69d2ea83 100644
--- a/quad/xsdk_workspace_vivado/real_quad/.project
+++ b/quad/xsdk_workspace_vivado/real_quad/.project
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>real_quad</name>
- <comment></comment>
+ <comment>Created by SDK v2018.2. system_bsp - ps7_cortexa9_0</comment>
<projects>
<project>system_bsp</project>
</projects>
@@ -32,7 +32,7 @@
<link>
<name>ext/computation_graph</name>
<type>2</type>
- <locationURI>QUAD_LOC/src/computation_graph</locationURI>
+ <location>/local/ucart/MicroCART/quad/src/computation_graph</location>
</link>
<link>
<name>ext/graph_blocks</name>
@@ -42,26 +42,44 @@
<link>
<name>ext/quad_app</name>
<type>2</type>
- <locationURI>QUAD_LOC/src/quad_app</locationURI>
+ <location>/local/ucart/MicroCART/quad/src/quad_app</location>
</link>
<link>
<name>ext/queue</name>
<type>2</type>
- <locationURI>QUAD_LOC/src/queue</locationURI>
+ <location>/local/ucart/MicroCART/quad/src/queue</location>
</link>
</linkedResources>
<filteredResources>
<filter>
- <id>1512949820706</id>
- <name></name>
+ <id>1539639053206</id>
+ <name>ext/commands</name>
+ <type>5</type>
+ <matcher>
+ <id>org.eclipse.ui.ide.multiFilter</id>
+ <arguments>1.0-name-matches-false-false-*.c</arguments>
+ </matcher>
+ </filter>
+ <filter>
+ <id>1539639053211</id>
+ <name>ext/commands</name>
+ <type>5</type>
+ <matcher>
+ <id>org.eclipse.ui.ide.multiFilter</id>
+ <arguments>1.0-name-matches-false-false-*.h</arguments>
+ </matcher>
+ </filter>
+ <filter>
+ <id>1539639053214</id>
+ <name>ext/commands</name>
<type>10</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-obj</arguments>
+ <arguments>1.0-name-matches-false-false-*</arguments>
</matcher>
</filter>
<filter>
- <id>0</id>
+ <id>1539639034966</id>
<name>ext/computation_graph</name>
<type>5</type>
<matcher>
@@ -70,7 +88,7 @@
</matcher>
</filter>
<filter>
- <id>0</id>
+ <id>1539639034970</id>
<name>ext/computation_graph</name>
<type>5</type>
<matcher>
@@ -79,7 +97,7 @@
</matcher>
</filter>
<filter>
- <id>0</id>
+ <id>1539639034973</id>
<name>ext/computation_graph</name>
<type>10</type>
<matcher>
@@ -88,7 +106,34 @@
</matcher>
</filter>
<filter>
- <id>0</id>
+ <id>1539639011807</id>
+ <name>ext/graph_blocks</name>
+ <type>5</type>
+ <matcher>
+ <id>org.eclipse.ui.ide.multiFilter</id>
+ <arguments>1.0-name-matches-false-false-*.c</arguments>
+ </matcher>
+ </filter>
+ <filter>
+ <id>1539639011810</id>
+ <name>ext/graph_blocks</name>
+ <type>5</type>
+ <matcher>
+ <id>org.eclipse.ui.ide.multiFilter</id>
+ <arguments>1.0-name-matches-false-false-*.h</arguments>
+ </matcher>
+ </filter>
+ <filter>
+ <id>1539639011815</id>
+ <name>ext/graph_blocks</name>
+ <type>10</type>
+ <matcher>
+ <id>org.eclipse.ui.ide.multiFilter</id>
+ <arguments>1.0-name-matches-false-false-*</arguments>
+ </matcher>
+ </filter>
+ <filter>
+ <id>1539638989698</id>
<name>ext/quad_app</name>
<type>5</type>
<matcher>
@@ -97,7 +142,7 @@
</matcher>
</filter>
<filter>
- <id>0</id>
+ <id>1539638989701</id>
<name>ext/quad_app</name>
<type>5</type>
<matcher>
@@ -106,7 +151,7 @@
</matcher>
</filter>
<filter>
- <id>0</id>
+ <id>1539638989706</id>
<name>ext/quad_app</name>
<type>10</type>
<matcher>
@@ -115,7 +160,7 @@
</matcher>
</filter>
<filter>
- <id>0</id>
+ <id>1539638949606</id>
<name>ext/queue</name>
<type>5</type>
<matcher>
@@ -124,28 +169,22 @@
</matcher>
</filter>
<filter>
- <id>0</id>
+ <id>1539638949607</id>
<name>ext/queue</name>
- <type>5</type>
+ <type>10</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*.h</arguments>
+ <arguments>1.0-name-matches-false-false-*</arguments>
</matcher>
</filter>
<filter>
- <id>0</id>
+ <id>1539638949610</id>
<name>ext/queue</name>
- <type>10</type>
+ <type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
- <arguments>1.0-name-matches-false-false-*</arguments>
+ <arguments>1.0-name-matches-false-false-*.h</arguments>
</matcher>
</filter>
</filteredResources>
- <variableList>
- <variable>
- <name>QUAD_LOC</name>
- <value>$%7BPARENT-1-WORKSPACE_LOC%7D</value>
- </variable>
- </variableList>
</projectDescription>
diff --git a/quad/xsdk_workspace_vivado/recorder_test/src/Xilinx.spec b/quad/xsdk_workspace_vivado/real_quad/src/Xilinx.spec
similarity index 100%
rename from quad/xsdk_workspace_vivado/recorder_test/src/Xilinx.spec
rename to quad/xsdk_workspace_vivado/real_quad/src/Xilinx.spec
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.c
index 43515c5d0..4ebdef185 100644
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.c
+++ b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.c
@@ -64,15 +64,6 @@ struct TimerDriver create_zybo_global_timer() {
global_timer.read = zybo_global_timer_read;
return global_timer;
}
-//
-//struct TimerDriver create_zybo_axi_timer() {
-// struct TimerDriver axi_timer;
-// axi_timer.state = NULL;
-// //axi_timer.reset = zybo_axi_timer_reset;
-// axi_timer.restart = zybo_axi_timer_restart;
-// axi_timer.read = zybo_axi_timer_read;
-// return axi_timer;
-//}
struct LEDDriver create_zybo_mio7_led() {
struct LEDDriver mio7_led;
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_tests.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_tests.c
index 4b3942ea7..f7d1bb2f1 100644
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_tests.c
+++ b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_tests.c
@@ -209,41 +209,6 @@ int test_zybo_motors() {
return 0;
}
-/**
- * Test for the AXI timer, using LEDDriver.
- *
- * This is essentially a basic "blink" program, using the mio7 LED
- * on the Zybo board.
- *
- * Instructions:
- * 1) Connect Zybo board to computer by USB cable.
- * 2) Set the RUN_TESTS macro in main.c
- * 3) Uncomment only this test in main.c
- * 4) Run main.c
- * 5) Observe MIO7 LED on board blinking at 1 second intervals.
- */
-//int test_zybo_axi_timer() {
-// //struct TimerDriver axi = create_zybo_axi_timer();
-// struct LEDDriver led = create_zybo_mio7_led();
-// //axi.reset(&axi);
-// led.reset(&led);
-//
-// unsigned long time;
-//
-// while (1) {
-// //axi.restart(&axi);
-// time = 0;
-// while (time < 1000000) {
-// axi.read(&axi, &time);
-// }
-// led.turn_off(&led);
-// while (time < 2000000) {
-// axi.read(&axi, &time);
-// }
-// led.turn_on(&led);
-// }
-//}
-
/**
* Test for the Global timer, using LEDDriver.
*
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/main.c b/quad/xsdk_workspace_vivado/real_quad/src/main.c
index 716a876a9..a71c754a7 100644
--- a/quad/xsdk_workspace_vivado/real_quad/src/main.c
+++ b/quad/xsdk_workspace_vivado/real_quad/src/main.c
@@ -29,7 +29,6 @@ int setup_hardware(hardware_t *hardware) {
hardware->comm = create_zybo_comm(&hardware->uart_0);
hardware->gps = create_zybo_gps(&hardware->uart_1);
hardware->global_timer = create_zybo_global_timer();
- //hardware->axi_timer = create_zybo_axi_timer();
hardware->mio7_led = create_zybo_mio7_led();
hardware->sys = create_zybo_system();
hardware->i2c_0 = create_zybo_i2c(0);
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/.cproject b/quad/xsdk_workspace_vivado/real_quad_fresh/.cproject
deleted file mode 100644
index 797766186..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/.cproject
+++ /dev/null
@@ -1,202 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
- <storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="xilinx.gnu.arm.exe.debug.980189137">
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.arm.exe.debug.980189137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
- <externalSettings/>
- <extensions>
- <extension id="com.xilinx.sdk.managedbuilder.XELF.arm" point="org.eclipse.cdt.core.BinaryParser"/>
- <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- </extensions>
- </storageModule>
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="xilinx.gnu.arm.exe.debug.980189137" name="Debug" parent="xilinx.gnu.arm.exe.debug">
- <folderInfo id="xilinx.gnu.arm.exe.debug.980189137." name="/" resourcePath="">
- <toolChain id="xilinx.gnu.arm.exe.debug.toolchain.1195127676" name="Xilinx ARM GNU Toolchain" resourceTypeBasedDiscovery="true" superClass="xilinx.gnu.arm.exe.debug.toolchain">
- <targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm" id="xilinx.arm.target.gnu.base.debug.2072264921" isAbstract="false" name="Debug Platform" superClass="xilinx.arm.target.gnu.base.debug"/>
- <builder buildPath="${workspace_loc:/modular_quad_pid}/Debug" enableAutoBuild="true" id="xilinx.gnu.arm.toolchain.builder.debug.2124876787" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU make" superClass="xilinx.gnu.arm.toolchain.builder.debug"/>
- <tool id="xilinx.gnu.arm.c.toolchain.assembler.debug.192056667" name="ARM gcc assembler" superClass="xilinx.gnu.arm.c.toolchain.assembler.debug">
- <inputType id="xilinx.gnu.assembler.input.532832448" superClass="xilinx.gnu.assembler.input"/>
- </tool>
- <tool id="xilinx.gnu.arm.c.toolchain.compiler.debug.177835003" name="ARM gcc compiler" superClass="xilinx.gnu.arm.c.toolchain.compiler.debug">
- <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.1900496019" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" value="gnu.c.optimization.level.none" valueType="enumerated"/>
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- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.2123463819" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath"/>
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diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/.gitignore b/quad/xsdk_workspace_vivado/real_quad_fresh/.gitignore
deleted file mode 100644
index 8274dfc9f..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/.gitignore
+++ /dev/null
@@ -1,7 +0,0 @@
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deleted file mode 100644
index 3c4c0ec69..000000000
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+++ /dev/null
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deleted file mode 100644
index 8e0550446..000000000
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diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/README.md b/quad/xsdk_workspace_vivado/real_quad_fresh/README.md
deleted file mode 100644
index 88089fe73..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/README.md
+++ /dev/null
@@ -1,10 +0,0 @@
-# The Real Quad
-_It is real, because it flies._
-
-Welcome to the most lame README in MicroCART. Everything we are about to say
-has already been said elsewhere, including [Our quad folder README][1], [xsdk_workspace README][2], and [HOW_TO_USE_XSDK markdown][3].
-So we aren't saying it here. Hence, this README is pretty empty. Hence... lame.
-
-[1]: ../README.md
-[2]: ../../README.md
-[3]: ../../doc/how_to_use_XSDK.md
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/ext/__CAUTION__.md b/quad/xsdk_workspace_vivado/real_quad_fresh/ext/__CAUTION__.md
deleted file mode 100644
index 6f7e2a00f..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/ext/__CAUTION__.md
+++ /dev/null
@@ -1,12 +0,0 @@
-****************************************
- Do not edit files in this directory!
-****************************************
-
-The fine print
-----
-
-Files in this directory are simlinked to external libraries. They exist here
-purely to help fascilitate the build process and permit debugging of those
-libraries within XSDK. Editing them here might build within XSDK, but it might
-break in its original context. Hence, don't edit these files within XSDK. Edit
-them within a workflow that uses the Makefile in the top-level quad folder.
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo.c
deleted file mode 100644
index fdc34f8ac..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo.c
+++ /dev/null
@@ -1,116 +0,0 @@
-#include "hw_impl_zybo.h"
-
-struct UARTDriver create_zybo_uart(int devId) {
- struct UARTDriver uart;
- uart.state = malloc(sizeof(struct ZyboUARTState));
- struct ZyboUARTState *state = uart.state;
- state->inst = malloc(sizeof(XUartPs));
- state->queue = queue_malloc(MAX_UART_BUFFER_SIZE);
- state->devId = devId;
-
- uart.reset = zybo_uart_reset;
- uart.write = zybo_uart_write;
- uart.read = zybo_uart_read;
- return uart;
-}
-
-struct GPSDriver create_zybo_gps(struct UARTDriver *uart) {
- struct GPSDriver gps;
- gps.uart = uart;
- gps.reset = zybo_gps_reset;
- gps.read = zybo_gps_read;
- return gps;
-}
-
-struct CommDriver create_zybo_comm(struct UARTDriver *uart) {
- struct CommDriver comm;
- comm.uart = uart;
- return comm;
-}
-
-struct MotorDriver create_zybo_motors() {
- struct MotorDriver motors;
- motors.state = NULL;
- motors.reset = zybo_motor_reset;
- motors.write = zybo_motor_write;
- return motors;
-}
-
-struct RCReceiverDriver create_zybo_rc_receiver() {
- struct RCReceiverDriver rc_receiver;
- rc_receiver.state = NULL;
- rc_receiver.reset = zybo_rc_receiver_reset;
- rc_receiver.read = zybo_rc_receiver_read;
- return rc_receiver;
-}
-
-struct I2CDriver create_zybo_i2c(int busId) {
- struct I2CDriver i2c;
- i2c.state = malloc(sizeof(struct ZyboI2CState));
- struct ZyboI2CState *state = i2c.state;
- state->inst = malloc(sizeof(XIicPs));
- state->busId = busId;
- i2c.reset = zybo_i2c_reset;
- i2c.write = zybo_i2c_write;
- i2c.read = zybo_i2c_read;
- return i2c;
-}
-
-struct TimerDriver create_zybo_global_timer() {
- struct TimerDriver global_timer;
- global_timer.state = NULL;
- global_timer.reset = zybo_global_timer_reset;
- global_timer.restart = zybo_global_timer_restart;
- global_timer.read = zybo_global_timer_read;
- return global_timer;
-}
-
-//struct TimerDriver create_zybo_axi_timer() {
-// struct TimerDriver axi_timer;
-// axi_timer.state = NULL;
-// axi_timer.reset = zybo_axi_timer_reset;
-// axi_timer.restart = zybo_axi_timer_restart;
-// axi_timer.read = zybo_axi_timer_read;
-// return axi_timer;
-//}
-
-struct LEDDriver create_zybo_mio7_led() {
- struct LEDDriver mio7_led;
- mio7_led.state = NULL;
- mio7_led.reset = zybo_mio7_led_reset;
- mio7_led.turn_on = zybo_mio7_led_turn_on;
- mio7_led.turn_off = zybo_mio7_led_turn_off;
- return mio7_led;
-}
-
-struct SystemDriver create_zybo_system() {
- struct SystemDriver sys;
- sys.state = NULL;
- sys.reset = zybo_system_reset;
- sys.sleep = zybo_system_sleep;
- return sys;
-}
-
-struct IMUDriver create_zybo_imu(struct I2CDriver *i2c) {
- struct IMUDriver imu;
- imu.i2c = i2c;
- imu.reset = zybo_imu_reset;
- imu.read = zybo_imu_read;
- return imu;
-}
-
-struct LidarDriver create_zybo_lidar(struct I2CDriver *i2c) {
- struct LidarDriver lidar;
- lidar.i2c = i2c;
- lidar.reset = zybo_lidar_reset;
- lidar.read = zybo_lidar_read;
- return lidar;
-}
-
-struct OpticalFlowDriver create_zybo_optical_flow(struct I2CDriver *i2c) {
- struct OpticalFlowDriver of;
- of.i2c = i2c;
- of.reset = zybo_optical_flow_reset;
- of.read = zybo_optical_flow_read;
- return of;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo.h b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo.h
deleted file mode 100644
index d8738b71c..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo.h
+++ /dev/null
@@ -1,105 +0,0 @@
-#ifndef HW_IMPL_ZYBO
-#define HW_IMPL_ZYBO
-
-#include "hw_iface.h"
-
-#include <sleep.h>
-#include <stdlib.h>
-#include <xgpiops.h>
-#include "xiicps.h"
-#include "xparameters.h"
-#include "xgpiops.h"
-#include "xil_types.h"
-#include "xscugic.h"
-#include "xtime_l.h"
-#include "xuartps.h"
-#include "queue.h"
-#include "platform.h"
-#include "sleep.h"
-#include "type_def.h"
-
-// Ideally, these defines would only be in the optical flow file, but
-// i2c needs it for a certain hack
-#define PX4FLOW_DEVICE_ADDR 0x42
-#define PX4FLOW_QUAL_MIN (100)
-
-#define MAX_UART_BUFFER_SIZE 2048
-
-struct ZyboI2CState {
- XIicPs *inst;
- int busId;
-};
-
-struct ZyboUARTState {
- struct Queue *queue;
- XUartPs *inst;
- XScuGic xscugic;
- int devId;
-};
-
-int zybo_uart_reset(struct UARTDriver *self);
-int zybo_uart_write(struct UARTDriver *self, unsigned char c);
-int zybo_uart_read(struct UARTDriver *self, unsigned char *c);
-
-int zybo_motor_reset(struct MotorDriver *self);
-int zybo_motor_write(struct MotorDriver *self, unsigned int channel, float magnitude);
-
-int zybo_rc_receiver_reset(struct RCReceiverDriver *self);
-int zybo_rc_receiver_read(struct RCReceiverDriver *self, unsigned int channel, float *magnitude);
-
-int zybo_i2c_reset(struct I2CDriver *self);
-int zybo_i2c_write(struct I2CDriver *self,
- unsigned short device_addr,
- unsigned char *data,
- unsigned int length);
-int zybo_i2c_read(struct I2CDriver *self,
- unsigned short device_addr,
- unsigned char *buff,
- unsigned int length);
-
-int zybo_global_timer_reset(struct TimerDriver *self);
-int zybo_global_timer_restart(struct TimerDriver *self);
-int zybo_global_timer_read(struct TimerDriver *self, u64 *us);
-
-int zybo_axi_timer_reset(struct TimerDriver *self);
-int zybo_axi_timer_restart(struct TimerDriver *self);
-int zybo_axi_timer_read(struct TimerDriver *self, u64 *us);
-
-int zybo_mio7_led_reset(struct LEDDriver *self);
-int zybo_mio7_led_turn_on(struct LEDDriver *self);
-int zybo_mio7_led_turn_off(struct LEDDriver *self);
-
-int zybo_system_reset(struct SystemDriver *self);
-int zybo_system_sleep(struct SystemDriver *self, unsigned long us);
-
-int zybo_imu_reset(struct IMUDriver *self, struct gam *gam);
-int zybo_imu_read(struct IMUDriver *self, struct gam *gam);
-
-int zybo_lidar_reset(struct LidarDriver *self, struct lidar *lidar);
-int zybo_lidar_read(struct LidarDriver *self, struct lidar *lidar);
-
-int zybo_optical_flow_reset(struct OpticalFlowDriver *self, struct px4flow *of);
-int zybo_optical_flow_read(struct OpticalFlowDriver *self, struct px4flow *of);
-
-int zybo_gps_reset(struct GPSDriver *self, gps_t *gps);
-int zybo_gps_read(struct GPSDriver *self, gps_t *gps);
-
-struct UARTDriver create_zybo_uart(int devId);
-struct CommDriver create_zybo_comm(struct UARTDriver *uart);
-struct GPSDriver create_zybo_gps(struct UARTDriver *uart);
-struct MotorDriver create_zybo_motors();
-struct RCReceiverDriver create_zybo_rc_receiver();
-struct I2CDriver create_zybo_i2c(int busId);
-struct TimerDriver create_zybo_global_timer();
-struct TimerDriver create_zybo_axi_timer();
-struct LEDDriver create_zybo_mio7_led();
-struct SystemDriver create_zybo_system();
-struct IMUDriver create_zybo_imu(struct I2CDriver *i2c);
-struct LidarDriver create_zybo_lidar(struct I2CDriver *i2c);
-struct OpticalFlowDriver create_zybo_optical_flow(struct I2CDriver *i2c);
-
-int test_zybo_i2c();
-int test_zybo_mio7_led_and_system();
-int test_zybo_rc_receivers();
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_global_timer.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_global_timer.c
deleted file mode 100644
index c1024a62f..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_global_timer.c
+++ /dev/null
@@ -1,18 +0,0 @@
-#include "hw_impl_zybo.h"
-
-int zybo_global_timer_reset(struct TimerDriver *self) {
- // Nothing to initialize
- return 0;
-}
-
-int zybo_global_timer_restart(struct TimerDriver *self) {
- XTime_SetTime(0);
- return 0;
-}
-
-int zybo_global_timer_read(struct TimerDriver *self, u64 *us) {
- XTime time;
- XTime_GetTime(&time);
- *us = ((u64)time * 1000000) / COUNTS_PER_SECOND; // (ticks)(1000000us/s)(s/ticks)
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_gps.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_gps.c
deleted file mode 100644
index ff495afdb..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_gps.c
+++ /dev/null
@@ -1,12 +0,0 @@
-#include "hw_iface.h"
-#include "hw_impl_zybo.h"
-
-int zybo_gps_reset(struct GPSDriver *self, gps_t *gps) {
- // TODO
- return -1;
-}
-
-int zybo_gps_read(struct GPSDriver *self, gps_t *gps) {
- // TODO
- return -1;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_i2c.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_i2c.c
deleted file mode 100644
index 751ae4ccf..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_i2c.c
+++ /dev/null
@@ -1,485 +0,0 @@
-#include "hw_impl_zybo.h"
-#include "xiicps.h"
-// System configuration registers
-// (Please see Appendix B: System Level Control Registers in the Zybo TRM)
-#define IIC_SYSTEM_CONTROLLER_RESET_REG_ADDR (0xF8000224)
-#define IO_CLK_CONTROL_REG_ADDR (0xF800012C)
-
-// Error code could be returned on an iic read if the watchdog timer triggers
-#define IIC_RX_TIMEOUT_FAILURE (-88)
-/*
-// IIC0 Registers
-#define IIC0_CONTROL_REG_ADDR (0xE0004000)
-#define IIC0_STATUS_REG_ADDR (0xE0004004)
-#define IIC0_SLAVE_ADDR_REG (0xE0004008)
-#define IIC0_DATA_REG_ADDR (0xE000400C)
-#define IIC0_INTR_STATUS_REG_ADDR (0xE0004010)
-#define IIC0_TRANFER_SIZE_REG_ADDR (0xE0004014)
-#define IIC0_INTR_EN (0xE0004024)
-#define IIC0_TIMEOUT_REG_ADDR (0xE000401C)
-*/
-//Interrupt Status Register Masks
-#define ARB_LOST (0x200)
-#define RX_UNF (0x80)
-#define TX_OVF (0x40)
-#define RX_OVF (0x20)
-#define SLV_RDY (0x10)
-#define TIME_OUT (0x08)
-#define NACK (0x04)
-#define MORE_DAT (0x02)
-#define TRANS_COMPLETE (0x01)
-
-#define WRITE_INTR_MASK (ARB_LOST | TIME_OUT | RX_OVF | TX_OVF | NACK)
-#define READ_INTR_MASK (ARB_LOST | TIME_OUT | RX_OVF | RX_UNF | NACK)
-
-#define IO_CLK_CONTROL_REG_ADDR (0xF800012C)
-#define I2C0_CPU_1XCLKACT (0x00040000)
-#define I2C1_CPU_1XCLKACT (0x00080000)
-
-int XIicPs_MasterSendPolled_ours(XIicPs *InstancePtr, u8 *MsgPtr,
- int ByteCount, u16 SlaveAddr);
-int XIicPs_MasterRecvPolled_ours(XIicPs *InstancePtr, u8 *MsgPtr,
- int ByteCount, u16 SlaveAddr);
-int XIicPs_SetupMaster(XIicPs *InstancePtr, int Role);
-
-int zybo_i2c_reset(struct I2CDriver *self) {
- // ensure all required memory is allocated
- struct ZyboI2CState *state = self->state;
- if (state == NULL) return -1;
- if (state->inst == NULL) return -1;
- if (state->busId > 1) return -1;
- int i2cID = state->busId;
- XIicPs *inst = state->inst;
-
- //Make sure CPU_1x clk is enabled fostatusr I2C controller
- u16 *aper_ctrl = (u16 *) IO_CLK_CONTROL_REG_ADDR;
- u32 aper_mask = (i2cID == 0) ? (I2C0_CPU_1XCLKACT) : (I2C1_CPU_1XCLKACT);
-
- if (*aper_ctrl & aper_mask){
- xil_printf("CPU_1x is set to I2C0\r\n");
- }
-
- else {
- xil_printf("CPU_1x is not set to I2C..Setting now\r\n");
- *aper_ctrl |= aper_mask;
- }
-
- // Look up
- XIicPs_Config *i2c_config = XIicPs_LookupConfig(i2cID);
- XStatus status = XIicPs_CfgInitialize(inst, i2c_config, i2c_config->BaseAddress);
-
- // Check if initialization was successful
- if(status != XST_SUCCESS){
- return -1;
- }
-
- // Reset the controller and set the clock to 400kHz
- XIicPs_Reset(inst);
- XIicPs_SetSClk(inst, 400000);
-
- return 0;
-}
-
-int zybo_i2c_write(struct I2CDriver *self,
- unsigned short device_addr,
- unsigned char *data,
- unsigned int length) {
- struct ZyboI2CState *state = self->state;
- XIicPs *inst = state->inst;
- if (device_addr == PX4FLOW_DEVICE_ADDR) {
- // If we are sending a request to optical flow, drop down to 100kHz
- XIicPs_SetSClk(inst, 100000);
- }
- int error = XIicPs_MasterSendPolled_ours(inst, data, length, device_addr);
- if (device_addr == PX4FLOW_DEVICE_ADDR) {
- // Put it back to 400kHz
- XIicPs_SetSClk(inst, 400000);
- }
- usleep(5);
- return error;
-}
-
-int zybo_i2c_read(struct I2CDriver *self,
- unsigned short device_addr,
- unsigned char *buff,
- unsigned int length) {
- struct ZyboI2CState *state = self->state;
- XIicPs *inst = state->inst;
- if (device_addr == PX4FLOW_DEVICE_ADDR) {
- // If we are sending a request to optical flow, drop down to 100kHz
- XIicPs_SetSClk(inst, 100000);
- }
- int error = XIicPs_MasterRecvPolled_ours(inst, buff, length, device_addr);
- if (device_addr == PX4FLOW_DEVICE_ADDR) {
- // Put it back to 400kHz
- XIicPs_SetSClk(inst, 400000);
- }
- usleep(5);
- return error;
-}
-
-/*****************************************************************************/
-/**
-* NOTE to MicroCART: This function is originally from the Xilinx library,
-* but we noticed that the original function didn't check for a NACK, which
-* would cause the original polling function to enter an infinite loop in the
-* event of a NACK. Notice that we have added that NACK check at the final
-* while loop of this function.
-*
-*
-* This function initiates a polled mode send in master mode.
-*u16 i2cID
-* It sends data to the FIFO and waits for the slave to pick them up.
-* If slave fails to remove data from FIFO, the send fails with
-* time out.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param MsgPtr is the pointer to the send buffer.
-* @param ByteCount is the number of bytes to be sent.
-* @param SlaveAddr is the address of the slave we are sending to.
-*
-* @return
-* - XST_SUCCESS if everything went well.
-* - XST_FAILURE if timed out.
-*
-* @note This send routine is for polled mode transfer only.
-*
-****************************************************************************/
-int XIicPs_MasterSendPolled_ours(XIicPs *InstancePtr, u8 *MsgPtr,
- int ByteCount, u16 SlaveAddr)
-{
- u32 IntrStatusReg;
- u32 StatusReg;
- u32 BaseAddr;
- u32 Intrs;
-
- /*
- * Assert validates the input arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(MsgPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
-
- BaseAddr = InstancePtr->Config.BaseAddress;
- InstancePtr->SendBufferPtr = MsgPtr;
- InstancePtr->SendByteCount = ByteCount;
-
- XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
-
- XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
-
- /*
- * Intrs keeps all the error-related interrupts.
- */
- Intrs = XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_TX_OVR_MASK |
- XIICPS_IXR_TO_MASK | XIICPS_IXR_NACK_MASK;
-
- /*
- * Clear the interrupt status register before use it to monitor.
- */
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
- /*
- * Transmit first FIFO full of data.
- */
- TransmitFifoFill(InstancePtr);
-
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
-
- /*
- * Continue sending as long as there is more data and
- * there are no errors.
- */
- while ((InstancePtr->SendByteCount > 0) &&
- ((IntrStatusReg & Intrs) == 0)) {
- StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-
- /*
- * Wait until transmit FIFO is empty.
- */
- if ((StatusReg & XIICPS_SR_TXDV_MASK) != 0) {
- IntrStatusReg = XIicPs_ReadReg(BaseAddr,
- XIICPS_ISR_OFFSET);
- continue;
- }
-
- /*
- * Send more data out through transmit FIFO.
- */
- TransmitFifoFill(InstancePtr);
- }
-
- /*
- * Check for completion of transfer.
- */
- // NOTE for MicroCART: Corrected function. Original left for reference.
-// while ((XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET) &
-// XIICPS_IXR_COMP_MASK) != XIICPS_IXR_COMP_MASK);
- while (!(IntrStatusReg & (Intrs | XIICPS_IXR_COMP_MASK))) {
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- }
-
- /*
- * If there is an error, tell the caller.
- */
- if (IntrStatusReg & Intrs) {
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-static XTime get_time() {
- XTime time;
- XTime_GetTime(&time);
- u64 us = (u64)time * (1000000 / COUNTS_PER_SECOND); // (ticks)(1000000us/s)(s/ticks)
- return us;
-}
-
-/*****************************************************************************/
-/**
-* This function initiates a polled mode receive in master mode.
-*
-* It repeatedly sets the transfer size register so the slave can
-* send data to us. It polls the data register for data to come in.
-* If slave fails to send us data, it fails with time out.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-* @param MsgPtr is the pointer to the receive buffer.
-* @param ByteCount is the number of bytes to be received.
-* @param SlaveAddr is the address of the slave we are receiving from.
-*
-* @return
-* - XST_SUCCESS if everything went well.
-* - XST_FAILURE if timed out.
-*
-* @note This receive routine is for polled mode transfer only.
-*
-****************************************************************************/
-int XIicPs_MasterRecvPolled_ours(XIicPs *InstancePtr, u8 *MsgPtr,
- int ByteCount, u16 SlaveAddr)
-{
- u32 IntrStatusReg;
- u32 Intrs;
- u32 StatusReg;
- u32 BaseAddr;
- int BytesToRecv;
- int BytesToRead;
- int TransSize;
- int Tmp;
-
- /*
- * Assert validates the input arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(MsgPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
-
- BaseAddr = InstancePtr->Config.BaseAddress;
- InstancePtr->RecvBufferPtr = MsgPtr;
- InstancePtr->RecvByteCount = ByteCount;
-
- XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
-
- XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
-
- /*
- * Intrs keeps all the error-related interrupts.
- */
- Intrs = XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_RX_OVR_MASK |
- XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_TO_MASK |
- XIICPS_IXR_NACK_MASK;
-
- /*
- * Clear the interrupt status register before use it to monitor.
- */
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
-
- /*
- * Set up the transfer size register so the slave knows how much
- * to send to us.
- */
- if (ByteCount > XIICPS_FIFO_DEPTH) {
- XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
- XIICPS_FIFO_DEPTH);
- }else {
- XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
- ByteCount);
- }
-
-/* <--- MicroCART additions (iic watchdog timer hack) ---> */
- u32 iic_freq = XIicPs_GetSClk(InstancePtr);
- // (1000000 * 9 / iic_freq) is the number of microseconds required to send 1 byte of data
- // Using 5 times as an upper bound
- u32 max_usec_per_byte = 5 * 1000000 * 9 / iic_freq;
- u64 start_time = get_time();
-/* <--- End hack ---> */
-
- /*
- * Pull the interrupt status register to find the errors.
- */
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- while ((InstancePtr->RecvByteCount > 0) &&
- ((IntrStatusReg & Intrs) == 0) && !(IntrStatusReg & XIICPS_IXR_COMP_MASK)) {
-/* <--- MicroCART additions (iic watchdog timer hack) ---> */
- u64 usec_passed = get_time() - start_time;
- // Add 1 so it has a chance to read
- if (usec_passed > max_usec_per_byte * (1 + ByteCount - InstancePtr->RecvByteCount)) {
- return IIC_RX_TIMEOUT_FAILURE;
- }
-/* <--- End hack ---> */
- StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-
- /*
- * If there is no data in the FIFO, check the interrupt
- * status register for error, and continue.
- */
- if ((StatusReg & XIICPS_SR_RXDV_MASK) == 0) {
- IntrStatusReg = XIicPs_ReadReg(BaseAddr,
- XIICPS_ISR_OFFSET);
- continue;
- }
-
- /*
- * The transfer size register shows how much more data slave
- * needs to send to us.
- */
- TransSize = XIicPs_ReadReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET);
-
- BytesToRead = InstancePtr->RecvByteCount;
-
- /*
- * If expected number of bytes is greater than FIFO size,
- * the master needs to wait for data comes in and set the
- * transfer size register for slave to send more.
- */
- if (InstancePtr->RecvByteCount > XIICPS_FIFO_DEPTH) {
- /* wait slave to send data */
- while ((TransSize > 2) &&
- ((IntrStatusReg & Intrs) == 0)) {
- TransSize = XIicPs_ReadReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET);
- IntrStatusReg = XIicPs_ReadReg(BaseAddr,
- XIICPS_ISR_OFFSET);
- }
-
- /*
- * If timeout happened, it is an error.
- */
- if (IntrStatusReg & XIICPS_IXR_TO_MASK) {
- return XST_FAILURE;
- }
- TransSize = XIicPs_ReadReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET);
-
- /*
- * Take trans size into account of how many more should
- * be received.
- */
- BytesToRecv = InstancePtr->RecvByteCount -
- XIICPS_FIFO_DEPTH + TransSize;
-
- /* Tell slave to send more to us */
- if (BytesToRecv > XIICPS_FIFO_DEPTH) {
- XIicPs_WriteReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET,
- XIICPS_FIFO_DEPTH);
- } else{
- XIicPs_WriteReg(BaseAddr,
- XIICPS_TRANS_SIZE_OFFSET, BytesToRecv);
- }
-
- BytesToRead = XIICPS_FIFO_DEPTH - TransSize;
- }
-
- Tmp = 0;
- IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
- while ((Tmp < BytesToRead) &&
- ((IntrStatusReg & Intrs) == 0)) {
- StatusReg = XIicPs_ReadReg(BaseAddr,
- XIICPS_SR_OFFSET);
- IntrStatusReg = XIicPs_ReadReg(BaseAddr,
- XIICPS_ISR_OFFSET);
-
- if ((StatusReg & XIICPS_SR_RXDV_MASK) == 0) {
- /* No data in fifo */
- continue;
- }
- XIicPs_RecvByte(InstancePtr);
- Tmp ++;
- }
- }
-
- if ((IntrStatusReg & Intrs) || InstancePtr->RecvByteCount > 0) {
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/*
-* NOTE to MicroCART: This function is required by the send polling method above,
-* but it was originally static, so we had to copy it word-for-word here.
-*
-* This function prepares a device to transfers as a master.
-*
-* @param InstancePtr is a pointer to the XIicPs instance.
-*
-* @param Role specifies whether the device is sending or receiving.
-*
-* @return
-* - XST_SUCCESS if everything went well.
-* - XST_FAILURE if bus is busy.
-*
-* @note Interrupts are always disabled, device which needs to use
-* interrupts needs to setup interrupts after this call.
-*
-****************************************************************************/
-int XIicPs_SetupMaster(XIicPs *InstancePtr, int Role)
-{
- u32 ControlReg;
- u32 BaseAddr;
- u32 EnabledIntr = 0x0;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- BaseAddr = InstancePtr->Config.BaseAddress;
- ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
-
-
- /*
- * Only check if bus is busy when repeated start option is not set.
- */
- if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0) {
- if (XIicPs_BusIsBusy(InstancePtr)) {
- return XST_FAILURE;
- }
- }
-
- /*
- * Set up master, AckEn, nea and also clear fifo.
- */
- ControlReg |= XIICPS_CR_ACKEN_MASK | XIICPS_CR_CLR_FIFO_MASK |
- XIICPS_CR_NEA_MASK | XIICPS_CR_MS_MASK;
-
- if (Role == RECVING_ROLE) {
- ControlReg |= XIICPS_CR_RD_WR_MASK;
- EnabledIntr = XIICPS_IXR_DATA_MASK |XIICPS_IXR_RX_OVR_MASK;
- }else {
- ControlReg &= ~XIICPS_CR_RD_WR_MASK;
- }
- EnabledIntr |= XIICPS_IXR_COMP_MASK | XIICPS_IXR_ARB_LOST_MASK;
-
- XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
-
- XIicPs_DisableAllInterrupts(BaseAddr);
-
- return XST_SUCCESS;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_imu.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_imu.c
deleted file mode 100644
index 31b68f49d..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_imu.c
+++ /dev/null
@@ -1,265 +0,0 @@
-#include "hw_iface.h"
-#include "hw_impl_zybo.h"
-#include "type_def.h"
-
-#include <string.h>
-
-#define MPU9150_DEVICE_ADDR 0b01101000
-#define MPU9150_COMPASS_ADDR 0x0C
-
-#define ACCEL_GYRO_READ_SIZE 14 //Bytes
-#define ACCEL_GYRO_BASE_ADDR 0x3B //Starting register address
-
-#define MAG_READ_SIZE 6
-#define MAG_BASE_ADDR 0x03
-
-#define MAG_DRDY_TIMEOUT (10)
-
-#define RAD_TO_DEG 57.29578
-#define DEG_TO_RAD 0.0174533
-
-// Array indicies when reading from ACCEL_GYRO_BASE_ADDR
-#define ACC_X_H 0
-#define ACC_X_L 1
-#define ACC_Y_H 2
-#define ACC_Y_L 3
-#define ACC_Z_H 4
-#define ACC_Z_L 5
-
-#define GYR_X_H 8
-#define GYR_X_L 9
-#define GYR_Y_H 10
-#define GYR_Y_L 11
-#define GYR_Z_H 12
-#define GYR_Z_L 13
-
-#define MAG_X_L 0
-#define MAG_X_H 1
-#define MAG_Y_L 2
-#define MAG_Y_H 3
-#define MAG_Z_L 4
-#define MAG_Z_H 5
-
-// Gyro is configured for +/-2000dps
-// Sensitivity gain is based off MPU9150 datasheet (pg. 11)
-#define GYRO_SENS 16.4
-
-#define GYRO_X_BIAS 0.005f
-#define GYRO_Y_BIAS -0.014f
-#define GYRO_Z_BIAS 0.0534//0.0541f
-
-#define ACCEL_X_BIAS 0.023f
-#define ACCEL_Y_BIAS 0.009f
-#define ACCEL_Z_BIAS 0.0686f
-
-int mpu9150_write(struct I2CDriver *i2c, u8 register_addr, u8 data);
-int mpu9150_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size);
-
-int mpu9150_calc_mag_sensitivity(struct IMUDriver *self, gam_t *gam);
-int mpu9150_read_mag(struct IMUDriver *self, gam_t* gam);
-int mpu9150_read_gyro_accel(gam_t* gam);
-
-int zybo_imu_reset(struct IMUDriver *self, gam_t *gam) {
- memset(gam, 0, sizeof(gam_t));
-
- struct I2CDriver *i2c = self->i2c;
-
- // Device Reset & Wake up
- mpu9150_write(i2c, 0x6B, 0x80);
- usleep(5000);
-
- // Set clock reference to Z Gyro
- mpu9150_write(i2c, 0x6B, 0x03);
- // Configure Digital Low/High Pass filter
- mpu9150_write(i2c, 0x1A,0x03); // Level 3 low pass on gyroscope
-
- // Configure Gyro to 2000dps, Accel. to +/-8G
- mpu9150_write(i2c, 0x1B, 0x18);
- mpu9150_write(i2c, 0x1C, 0x10);
-
- // Enable I2C bypass for AUX I2C (Magnetometer)
- mpu9150_write(i2c, 0x37, 0x02);
-
- usleep(100000);
-
- //Calculate magnetometer sensitivities
- mpu9150_calc_mag_sensitivity(self, gam);
-
- usleep(10000);
-
- //Enable single measurement mode
- mpu9150_write(i2c, 0x0A, 0x00);
- mpu9150_write(i2c, 0x0A, 0x01);
-
- int i;
-
- // Do about 20 reads to warm up the device
- for(i=0; i < 20; ++i){
- self->read(self, gam);
- usleep(1000);
- }
-
- return 0;
-}
-
-int mpu9150_calc_mag_sensitivity(struct IMUDriver *self, gam_t *gam) {
- u8 buf[3];
- u8 ASAX, ASAY, ASAZ;
-
- // Quickly read from the factory ROM to get correction coefficents
- int status = mpu9150_write(self->i2c, 0x0A, 0x0F);
- if(status != 0) {
- return status;
- }
-
- usleep(10000);
-
- // Read raw adjustment values
- status = mpu9150_read(self->i2c, buf, 0x10,3);
- if(status != 0) {
- return status;
- }
- ASAX = buf[0];
- ASAY = buf[1];
- ASAZ = buf[2];
-
- // Set the correction coefficients
- gam->magX_correction = (ASAX-128)*0.5/128 + 1;
- gam->magY_correction = (ASAY-128)*0.5/128 + 1;
- gam->magZ_correction = (ASAZ-128)*0.5/128 + 1;
-
- return 0;
-}
-
-int zybo_imu_read(struct IMUDriver *self, gam_t *gam) {
- struct I2CDriver *i2c = self->i2c;
- i16 raw_accel_x, raw_accel_y, raw_accel_z;
- i16 gyro_x, gyro_y, gyro_z;
-
- u8 sensor_data[ACCEL_GYRO_READ_SIZE] = {};
-
- int error = mpu9150_read(i2c, sensor_data, ACCEL_GYRO_BASE_ADDR, ACCEL_GYRO_READ_SIZE);
- if (error) return error;
-
- //Calculate accelerometer data
- raw_accel_x = sensor_data[ACC_X_H] << 8 | sensor_data[ACC_X_L];
- raw_accel_y = sensor_data[ACC_Y_H] << 8 | sensor_data[ACC_Y_L];
- raw_accel_z = sensor_data[ACC_Z_H] << 8 | sensor_data[ACC_Z_L];
-
- // put in G's
- gam->accel_x = (raw_accel_x / 4096.0) + ACCEL_X_BIAS; // 4,096 is the gain per LSB of the measurement reading based on a configuration range of +-8g
- gam->accel_y = (raw_accel_y / 4096.0) + ACCEL_Y_BIAS;
- gam->accel_z = (raw_accel_z / 4096.0) + ACCEL_Z_BIAS;
-
- //Convert gyro data to rate (we're only using the most 12 significant bits)
- gyro_x = (sensor_data[GYR_X_H] << 8) | (sensor_data[GYR_X_L]); //* G_GAIN;
- gyro_y = (sensor_data[GYR_Y_H] << 8 | sensor_data[GYR_Y_L]);// * G_GAIN;
- gyro_z = (sensor_data[GYR_Z_H] << 8 | sensor_data[GYR_Z_L]);// * G_GAIN;
-
- //Get the number of degrees
- //javey: converted to radians to following SI units
- gam->gyro_xVel_p = ((gyro_x / GYRO_SENS) * DEG_TO_RAD) + GYRO_X_BIAS;
- gam->gyro_yVel_q = ((gyro_y / GYRO_SENS) * DEG_TO_RAD) + GYRO_Y_BIAS;
- gam->gyro_zVel_r = ((gyro_z / GYRO_SENS) * DEG_TO_RAD) + GYRO_Z_BIAS;
-
- // Magnometer
- mpu9150_read_mag(self, gam);
-
- return error;
-}
-
-//////////////////////
-// Helper functions
-/////////////////////
-
-int mpu9150_write(struct I2CDriver *i2c, u8 register_addr, u8 data){
-
- u16 device_addr = MPU9150_DEVICE_ADDR;
- u8 buf[] = {register_addr, data};
-
- // Check if within register range
- if(register_addr < 0 || register_addr > 0x75){
- return -1;
- }
-
- if(register_addr <= 0x12){
- device_addr = MPU9150_COMPASS_ADDR;
- }
-
- return i2c->write(i2c, device_addr, buf, 2);
-}
-
-int mpu9150_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size){
-
- u16 device_addr = MPU9150_DEVICE_ADDR;
- u8 buf[] = {register_addr};
-
- // Check if within register range
- if(register_addr < 0 || register_addr > 0x75){
- }
-
- // Set device address to the if 0x00 <= register address <= 0x12
- if(register_addr <= 0x12){
- device_addr = MPU9150_COMPASS_ADDR;
- }
-
-
- int error = i2c->write(i2c, device_addr, buf, 1);
- if (error) return error;
- return i2c->read(i2c, device_addr, recv_buffer, size);
-}
-
-
-int mpu9150_read_mag(struct IMUDriver *self, gam_t* gam){
- u8 mag_data[6];
- u8 mag_status;
- i16 raw_magX, raw_magY, raw_magZ;
-
- int trigger = 0;
-
- int status = mpu9150_read(self->i2c, mag_data, 0x02, 1);
- if(status != 0) {
- return status;
- }
-
- if(mag_data[0] & 0x01) {
- // Get mag data
- status = mpu9150_read(self->i2c, mag_data, 0x03, 6);
- if(status != 0) {
- return status;
- }
-
- status = mpu9150_read(self->i2c, &mag_status, 0x09, 1);
- if(status != 0) {
- return status;
- }
-
- raw_magX = (mag_data[1] << 8) | mag_data[0];
- raw_magY = (mag_data[3] << 8) | mag_data[2];
- raw_magZ = (mag_data[5] << 8) | mag_data[4];
-
- // Set magnetometer data to output
- gam->mag_x = raw_magX * gam->magX_correction;
- gam->mag_y = raw_magY * gam->magY_correction;
- gam->mag_z = raw_magZ * gam->magZ_correction;
-
- trigger = 1;
- }
- else {
- gam->magDRDYCount++;
-
- if(gam->magDRDYCount > MAG_DRDY_TIMEOUT) {
- gam->magDRDYCount = 0;
-
- trigger = 1;
- }
- }
-
- if(trigger) {
- //Start next reading
- mpu9150_write(self->i2c, 0x0A, 0x00);
- mpu9150_write(self->i2c, 0x0A, 0x01);
- }
-
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_lidar.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_lidar.c
deleted file mode 100644
index 32d0fad0c..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_lidar.c
+++ /dev/null
@@ -1,68 +0,0 @@
-#include "hw_iface.h"
-#include "hw_impl_zybo.h"
-#include "type_def.h"
-#include <string.h>
-
-#define LIDARLITE_DEVICE_ADDR 0x62
-#define LIDAR_OFFSET (0.016666) // Distance from LiDAR sensor to ground, in meters
-
-int lidarlite_write(struct I2CDriver *i2c, u8 register_addr, u8 data);
-int lidarlite_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size);
-
-int zybo_lidar_reset(struct LidarDriver *self, lidar_t *lidar) {
- // initialize lidar
- memset(lidar, 0, sizeof(lidar_t));
-
- struct I2CDriver *i2c = self->i2c;
-
- int error = 0;
-
- // Device Reset & Wake up with default settings
- error = lidarlite_write(i2c, 0x00, 0x00);
- if (error) return error;
- usleep(15000);
-
- // Enable Free Running Mode and distance measurements with correction
- error = lidarlite_write(i2c, 0x11, 0xff);
- if (error) return error;
- error = lidarlite_write(i2c, 0x00, 0x04);
- return error;
-}
-
-int zybo_lidar_read(struct LidarDriver *self, lidar_t *lidar) {
- struct I2CDriver *i2c = self->i2c;
- u8 buf[2];
- int error = 0;
-
- // Read the sensor value
- error = lidarlite_read(i2c, buf, 0x8f, 2);
- if (error) return error;
- float distance_cm = (float)(buf[0] << 8 | buf[1]);
- lidar->distance_m = (distance_cm * 0.01) + LIDAR_OFFSET;
-
- return error;
-}
-
-////////////////////
-// Helper functions
-////////////////////
-
-int lidarlite_write(struct I2CDriver *i2c, u8 register_addr, u8 data) {
- u8 buf[] = {register_addr, data};
- return i2c->write(i2c, LIDARLITE_DEVICE_ADDR, buf, 2);
-}
-
-int lidarlite_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size) {
- u8 buf[] = {register_addr};
- int error = 0;
-
- error = i2c->write(i2c, LIDARLITE_DEVICE_ADDR, buf, 1);
- if (error) return error;
- error = i2c->read(i2c, LIDARLITE_DEVICE_ADDR, recv_buffer, size);
- return error;
-}
-
-// Maybe this will be useful?
-int lidarlite_sleep(struct I2CDriver *i2c) {
- return lidarlite_write(i2c, 0x65, 0x84);
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_mio7_led.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_mio7_led.c
deleted file mode 100644
index 03a192671..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_mio7_led.c
+++ /dev/null
@@ -1,22 +0,0 @@
-#include "hw_impl_zybo.h"
-
-int zybo_mio7_led_reset(struct LEDDriver *self) {
- if (self->state == NULL) {
- self->state = malloc(sizeof(XGpioPs));
- }
-
- XGpioPs_Config *ConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
- XGpioPs_CfgInitialize(self->state, ConfigPtr, ConfigPtr->BaseAddr);
- XGpioPs_SetDirectionPin(self->state, 7, 1);
- return 0;
-}
-
-int zybo_mio7_led_turn_on(struct LEDDriver *self) {
- XGpioPs_WritePin(self->state, 7, 0x01);
- return 0;
-}
-
-int zybo_mio7_led_turn_off(struct LEDDriver *self) {
- XGpioPs_WritePin(self->state, 7, 0x00);
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_motor.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_motor.c
deleted file mode 100644
index 8e8e27ab7..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_motor.c
+++ /dev/null
@@ -1,55 +0,0 @@
-#include "hw_impl_zybo.h"
-
-#define SYS_CLOCK_RATE 100000000 // ticks per second
-#define FREQUENCY 450
-#define PERIOD_WIDTH SYS_CLOCK_RATE/FREQUENCY
-#define PULSE_WIDTH_LOW SYS_CLOCK_RATE/1000 // 1 ms
-#define PULSE_WIDTH_HIGH SYS_CLOCK_RATE/500 // 2 ms
-#define PULSE_WIDTH_ADDR_OFFSET 1
-
-struct MotorDriverState {
- int *outputs[4];
-};
-
-int zybo_motor_reset(struct MotorDriver *self) {
- if (self->state == NULL) {
- self->state = malloc(sizeof(struct MotorDriverState));
- if (self->state == NULL) {
- return -1;
- }
- }
- struct MotorDriverState *state = self->state;
-
- state->outputs[0] = (int *) XPAR_PWM_SIGNAL_OUT_0_S_AXI_BASEADDR;
- state->outputs[1] = (int *) XPAR_PWM_SIGNAL_OUT_1_S_AXI_BASEADDR;
- state->outputs[2] = (int *) XPAR_PWM_SIGNAL_OUT_2_S_AXI_BASEADDR;
- state->outputs[3] = (int *) XPAR_PWM_SIGNAL_OUT_3_S_AXI_BASEADDR;
-
- // Set period width of PWM pulse
- *(state->outputs[0]) = PERIOD_WIDTH;
- *(state->outputs[1]) = PERIOD_WIDTH;
- *(state->outputs[2]) = PERIOD_WIDTH;
- *(state->outputs[3]) = PERIOD_WIDTH;
-
- // Set a low pulse (1 ms) so that outputs are off
- *(state->outputs[0] + PULSE_WIDTH_ADDR_OFFSET) = PULSE_WIDTH_LOW;
- *(state->outputs[1] + PULSE_WIDTH_ADDR_OFFSET) = PULSE_WIDTH_LOW;
- *(state->outputs[2] + PULSE_WIDTH_ADDR_OFFSET) = PULSE_WIDTH_LOW;
- *(state->outputs[3] + PULSE_WIDTH_ADDR_OFFSET) = PULSE_WIDTH_LOW;
-
- usleep(1000000);
- return 0;
-}
-
-int zybo_motor_write(struct MotorDriver *self,
- unsigned int channel,
- float magnitude) {
- if (magnitude > 1)
- magnitude = 1;
- if (magnitude < 0)
- magnitude = 0;
- struct MotorDriverState *state = self->state;
- unsigned long pulse_width_ticks = (unsigned long) (magnitude * (float) (PULSE_WIDTH_HIGH - PULSE_WIDTH_LOW)) + PULSE_WIDTH_LOW;
- *(state->outputs[channel] + PULSE_WIDTH_ADDR_OFFSET) = pulse_width_ticks;
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_optical_flow.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_optical_flow.c
deleted file mode 100644
index c45ca68a9..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_optical_flow.c
+++ /dev/null
@@ -1,74 +0,0 @@
-#include "hw_iface.h"
-#include "hw_impl_zybo.h"
-#include <stdint.h>
-#include <string.h>
-#include "type_def.h"
-
-int px4flow_write(struct I2CDriver *i2c, u8 register_addr, u8 data);
-int px4flow_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size);
-
-int zybo_optical_flow_reset(struct OpticalFlowDriver *self, px4flow_t *of) {
- memset(of, 0, sizeof(px4flow_t));
-
- return 0;
-}
-
-int zybo_optical_flow_read(struct OpticalFlowDriver *self, px4flow_t *of) {
- struct I2CDriver *i2c = self->i2c;
- int error = 0;
-
- // Note: Despite documentation, do not mark this as a "packed" struct. The actual code does not pack it.
- struct i2c_integral_frame
- {
- uint16_t frame_count_since_last_readout;//number of flow measurements since last I2C readout [#frames]
- int16_t pixel_flow_x_integral;//accumulated flow in radians*10000 around x axis since last I2C readout [rad*10000]
- int16_t pixel_flow_y_integral;//accumulated flow in radians*10000 around y axis since last I2C readout [rad*10000]
- int16_t gyro_x_rate_integral;//accumulated gyro x rates in radians*10000 since last I2C readout [rad*10000]
- int16_t gyro_y_rate_integral;//accumulated gyro y rates in radians*10000 since last I2C readout [rad*10000]
- int16_t gyro_z_rate_integral;//accumulated gyro z rates in radians*10000 since last I2C readout [rad*10000]
- uint32_t integration_timespan;//accumulation timespan in microseconds since last I2C readout [microseconds]
- uint32_t sonar_timestamp;// time since last sonar update [microseconds]
- int16_t ground_distance;// Ground distance in meters*1000 [meters*1000]
- int16_t gyro_temperature;// Temperature * 100 in centi-degrees Celsius [degcelsius*100]
- uint8_t quality;// averaged quality of accumulated flow values [0:bad quality;255: max quality]
- } i2c_integral_frame;
-
- u8 buf[sizeof(i2c_integral_frame)];
-
- // Read the sensor value
- error = px4flow_read(i2c, buf, 0x16, 26);
-
- if(error == 0) {
- //Copy into struct
- memcpy(&i2c_integral_frame, buf, sizeof(i2c_integral_frame));
-
- of->flow_x_rad = 0.0001 * i2c_integral_frame.pixel_flow_x_integral;
- of->flow_y_rad = 0.0001 * i2c_integral_frame.pixel_flow_y_integral;
- of->quality = i2c_integral_frame.quality;
- of->dt = (double)i2c_integral_frame.integration_timespan / 1000000;
- }
- return error;
-}
-
-/////////////////////
-// Helper functions
-/////////////////////
-
-int px4flow_write(struct I2CDriver *i2c, u8 register_addr, u8 data) {
- u8 buf[] = {register_addr, data};
-
- return i2c->write(i2c, PX4FLOW_DEVICE_ADDR, buf, 2);
-}
-
-int px4flow_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size) {
- u8 buf[] = {register_addr};
- int error = 0;
-
- error = i2c->write(i2c, PX4FLOW_DEVICE_ADDR, buf, 1);
- if (error) {
- return error;
- }
- error = i2c->read(i2c, PX4FLOW_DEVICE_ADDR, recv_buffer, size);
- return error;
-}
-
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_rc_receiver.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_rc_receiver.c
deleted file mode 100644
index 391333b0a..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_rc_receiver.c
+++ /dev/null
@@ -1,40 +0,0 @@
-#include "hw_impl_zybo.h"
-
-#define SYS_CLOCK_RATE 100000000 // ticks per second
-#define FREQUENCY 450
-#define PERIOD_WIDTH SYS_CLOCK_RATE/FREQUENCY
-#define PULSE_WIDTH_LOW SYS_CLOCK_RATE/1000 // 1 ms
-#define PULSE_WIDTH_HIGH SYS_CLOCK_RATE/500 // 2 ms
-#define PULSE_WIDTH_ADDR_OFFSET 1
-
-struct RCReceiverDriverState {
- int *channels[6];
-};
-
-int zybo_rc_receiver_reset(struct RCReceiverDriver *self) {
- if (self->state == NULL) {
- self->state = malloc(sizeof(struct RCReceiverDriverState));
- if (self->state == NULL) {
- return -1;
- }
- }
-
- // Save the addresses of the input PWM recorders
- struct RCReceiverDriverState *state = self->state;
- state->channels[0] = (int *) XPAR_PWM_RECORDER_0_S_AXI_BASEADDR;
- state->channels[1] = (int *) XPAR_PWM_RECORDER_1_S_AXI_BASEADDR;
- state->channels[2] = (int *) XPAR_PWM_RECORDER_2_S_AXI_BASEADDR;
- state->channels[3] = (int *) XPAR_PWM_RECORDER_3_S_AXI_BASEADDR;
- state->channels[4] = (int *) XPAR_PWM_RECORDER_4_S_AXI_BASEADDR;
- state->channels[5] = (int *) XPAR_PWM_RECORDER_5_S_AXI_BASEADDR;
- return 0;
-}
-
-int zybo_rc_receiver_read(struct RCReceiverDriver *self,
- unsigned int channel,
- float *magnitude) {
- struct RCReceiverDriverState *state = self->state;
- unsigned long pulse_width_ticks = (long) *((int *) state->channels[channel]);
- *magnitude = (float) (pulse_width_ticks - PULSE_WIDTH_LOW) / (float) (PULSE_WIDTH_HIGH - PULSE_WIDTH_LOW);
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_system.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_system.c
deleted file mode 100644
index 2adcc4007..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_system.c
+++ /dev/null
@@ -1,11 +0,0 @@
-#include "hw_impl_zybo.h"
-
-int zybo_system_reset(struct SystemDriver *sys) {
- return 0;
-}
-
-int zybo_system_sleep(struct SystemDriver *sys, unsigned long us) {
- usleep(us);
- return 0;
-}
-
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_tests.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_tests.c
deleted file mode 100644
index 732c6256a..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_tests.c
+++ /dev/null
@@ -1,321 +0,0 @@
-#include "hw_impl_zybo.h"
-#include "type_def.h"
-#include <stdio.h>
-
-/**
- * Test for the LEDDriver and SystemDriver.
- *
- * This is essentially a basic "blink" program, using the mio7 LED
- * on the Zybo board.
- *
- * Instructions:
- * 1) Connect Zybo board to computer by USB cable.
- * 2) Set the RUN_TESTS macro in main.c
- * 3) Uncomment only this test in main.c
- * 4) Run main.c
- * 5) Observe MIO7 LED on board blinking at 1 second intervals.
- */
-int test_zybo_mio7_led_and_system() {
- struct LEDDriver mio7 = create_zybo_mio7_led();
- struct SystemDriver sys = create_zybo_system();
- mio7.reset(&mio7);
- sys.reset(&sys);
-
- while (1) {
- mio7.turn_on(&mio7);
- sys.sleep(&sys, 1000000);
- mio7.turn_off(&mio7);
- sys.sleep(&sys, 1000000);
- }
-
- return 0;
-}
-
-/**
- * Tests for the I2CDriver (one for each I2C device we use)
- *
- * Instructions:
- * 1) Connect Zybo Board to computer by USB cable.
- * 2) Prepare a breadboard to accomplish the following connections:
- * - Zybo GND <-> LIDAR GND
- * - Zybo WALL <-> LIDAR VCC
- * - Zybo VV5V0 <-> LIDAR VCC
- * - Zybo SDA/SCL <-> LIDAR SDA/SCL
- * - The Zybo I2C SCL and SDA pins are on pins 1 and 2 of PORT JF, respectively
- * 3) Place breakpoint in this test function, somewhere in the while loop.
- * 4) Set the RUN_TESTS macro in main.c
- * 5) Uncomment only this test in main.c
- * 6) Debug main.c
- * 7) Step through the while loop, observing x change as you physically change the
- * distance of the LIDAR sensor.
- */
-int test_zybo_i2c() {
- struct I2CDriver i2c = create_zybo_i2c(0);
- struct LidarDriver ld = create_zybo_lidar(&i2c);
- i2c.reset(&i2c);
-
- lidar_t lidar = { };
- if (ld.reset(&ld, &lidar)) return 0;
- while (1) {
- ld.read(&ld, &lidar);
- }
- return 0;
-}
-
-int test_zybo_i2c_imu() {
- struct I2CDriver i2c = create_zybo_i2c(0);
- struct IMUDriver imu = create_zybo_imu(&i2c);
-
- gam_t gam;
- if (i2c.reset(&i2c)) return 0;
- if (imu.reset(&imu, &gam)) return 0;
-
- int status = 0;
- while (!status) {
- status = imu.read(&imu, &gam);
- }
- return 0;
-}
-
-int test_zybo_i2c_px4flow() {
- struct I2CDriver i2c = create_zybo_i2c(0);
- struct OpticalFlowDriver ofd = create_zybo_optical_flow(&i2c);
- i2c.reset(&i2c);
- px4flow_t of;
-
- if (ofd.reset(&ofd, &of)) return 0;
-
- int status = 0;
- while(!status) {
- usleep(5000);
- status = ofd.read(&ofd, &of);
- }
-
- return 0;
-}
-
-int test_zybo_i2c_lidar() {
- struct I2CDriver i2c = create_zybo_i2c(1);
- struct LidarDriver lidarDriver = create_zybo_lidar(&i2c);
- i2c.reset(&i2c);
- lidar_t lidar;
-
- if (lidarDriver.reset(&lidarDriver, &lidar))
- return 0;
-
- int status = 0;
- while(!status) {
- usleep(5000);
- status = lidarDriver.read(&lidarDriver, &lidar);
- }
-
- return 0;
-}
-
-int test_zybo_i2c_all() {
- struct I2CDriver i2c_0 = create_zybo_i2c(0);
- struct IMUDriver imu = create_zybo_imu(&i2c_0);
- struct I2CDriver i2c_1 = create_zybo_i2c(1);
- struct LidarDriver ld = create_zybo_lidar(&i2c_1);
- struct OpticalFlowDriver ofd = create_zybo_optical_flow(&i2c_0);
- i2c_0.reset(&i2c_0);
- i2c_1.reset(&i2c_1);
-
- lidar_t lidar;
- px4flow_t of;
- gam_t gam;
-
- if (ld.reset(&ld, &lidar)) return 0;
- if (imu.reset(&imu, &gam)) return 0;
- if (ofd.reset(&ofd, &of)) return 0;
-
-
- int lidarErrors = 0;
- int gamErrors = 0;
- int nLoops = 0;
- int of_errors = 0;
-
- for(;;) {
- ld.read(&ld, &lidar);
- imu.read(&imu, &gam);
- ofd.read(&ofd, &of);
-
- if (lidar.distance_m > 50) {
- lidarErrors += 1;
- }
- if (gam.accel_z > -0.8) {
- gamErrors += 1;
- }
- nLoops += 1;
- }
- return 0;
-}
-
-/**
- * Test for the PWMInputDriver.
- *
- * Instructions:
- * 1) Connect the quad Zybo board to computer using USB.
- * 2) Move jumper on Zybo board to use JTAG instead of SD.
- * 3) Turn on Zybo board and turn on Spektrum handheld controller.
- * - Verify receiver on quad pairs with controller (orange LED should turn on)
- * 3) Place breakpoint somewhere in the while loop of this function.
- * 4) Set the RUN_TESTS macro in main.c
- * 5) Uncomment only this test in main.c
- * 6) Debug main.
- * 7) Observe the values of pwm_inputs in debugger changing as you use the
- * Spektrum RC controller.
- */
-int test_zybo_rc_receiver() {
- struct RCReceiverDriver rc_receiver = create_zybo_rc_receiver();
- rc_receiver.reset(&rc_receiver);
-
- float pwms[6];
- while (1) {
- int i;
- for (i = 0; i < 6; i += 1) {
- rc_receiver.read(&rc_receiver, i, &pwms[i]);
- }
- continue;
- }
-}
-
-/**
- * Test for the PWMOutputDriver.
- *
- * Instructions:
- * 1) Connect the quad Zybo board to computer using USB.
- * 2) Move jumper on Zybo board to use JTAG instead of SD.
- * 3) Get an oscilloscope and observe PMOD outputs JE7-JE10
- * 4) Set the RUN_TESTS macro in main.c
- * 5) Uncomment only this test in main.c
- * 6) Run main.
- * 7) Observe the PWM width of those PMOD pins changing with time
- */
-int test_zybo_motors() {
- struct MotorDriver motors = create_zybo_motors();
- motors.reset(&motors);
-
- double j = 0;
- while (1) {
- for (j = 0; j < 1.0; j += 0.01) {
- int i = 0;
- for (i = 0; i < 4; i += 1) {
- motors.write(&motors, i, j);
- usleep(50000);
- }
- }
- }
- return 0;
-}
-
-/**
- * Test for the AXI timer, using LEDDriver.
- *
- * This is essentially a basic "blink" program, using the mio7 LED
- * on the Zybo board.
- *
- * Instructions:
- * 1) Connect Zybo board to computer by USB cable.
- * 2) Set the RUN_TESTS macro in main.c
- * 3) Uncomment only this test in main.c
- * 4) Run main.c
- * 5) Observe MIO7 LED on board blinking at 1 second intervals.
- */
-//int test_zybo_axi_timer() {
-// struct TimerDriver axi = create_zybo_axi_timer();
-// struct LEDDriver led = create_zybo_mio7_led();
-// axi.reset(&axi);
-// led.reset(&led);
-//
-// unsigned long time;
-//
-// while (1) {
-// axi.restart(&axi);
-// time = 0;
-// while (time < 1000000) {
-// axi.read(&axi, &time);
-// }
-// led.turn_off(&led);
-// while (time < 2000000) {
-// axi.read(&axi, &time);
-// }
-// led.turn_on(&led);
-// }
-//}
-
-/**
- * Test for the Global timer, using LEDDriver.
- *
- * This is essentially a basic "blink" program, using the mio7 LED
- * on the Zybo board.
- *
- * Instructions:
- * 1) Connect Zybo board to computer by USB cable.
- * 2) Set the RUN_TESTS macro in main.c
- * 3) Uncomment only this test in main.c
- * 4) Run main.c
- * 5) Observe MIO7 LED on board blinking at 1 second intervals.
- */
-int test_zybo_global_timer() {
- struct TimerDriver global = create_zybo_global_timer();
- struct LEDDriver led = create_zybo_mio7_led();
- global.reset(&global);
- led.reset(&led);
-
- unsigned long time;
-
- while (1) {
- global.restart(&global);
- time = 0;
- while (time < 1000000) {
- global.read(&global, &time);
- }
- led.turn_off(&led);
- while (time < 2000000) {
- global.read(&global, &time);
- }
- led.turn_on(&led);
- }
-}
-
-/**
- * Communication tests using the UARTDriver.
- *
- * Instructions:
- * 1) Connect Zybo board to computer by USB cable.
- * 2) Get a FTDI Basic Sparkfun board in order to connect the UART pins
- * on the Zybo to the computer by USB.
- * - Zybo PMOD JC2 (TX) <-> Sparkfun Board RX
- * - Zybo PMOD JC3 (RX) <-> sparkfun Board Tx
- * - Zybo PMOD JC5 (GND) <-> Sparkfun Board GDN
- * 2) Set the RUN_TESTS macro in main.c
- * 3) Uncomment only this test in main.c
- * 4) Run main.c
- * 5) Execute quad/scripts/tests/test_zybo_uart.py
- * - Observe test results on terminal
- * - You might be able to see LED MIO7 blink when it receives bytes
- */
-int test_zybo_uart_comm() {
- struct UARTDriver uart = create_zybo_uart(0);
- struct CommDriver comm = create_zybo_comm(&uart);
- struct LEDDriver led = create_zybo_mio7_led();
- uart.reset(&uart);
- led.reset(&led);
-
- unsigned char c;
- while (1) {
- if (comm.uart->read(comm.uart, &c)) {
- // read failed
- led.turn_off(&led);
- } else {
- // read successful
- led.turn_on(&led);
- uart.write(&uart, c);
- }
- }
-
- return 0;
-}
-
-
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_uart.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_uart.c
deleted file mode 100644
index 9d3ff7050..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_uart.c
+++ /dev/null
@@ -1,282 +0,0 @@
-#include "hw_impl_zybo.h"
-
-#define BAUD_RATE 921600
-
-
-int XUartPs_SetBaudRate_ours(XUartPs *InstancePtr, u32 BaudRate);
-int SetupInterruptSystem(struct ZyboUARTState *state, u16 UartIntrId, Xil_ExceptionHandler handler);
-void uart_interrupt_handler(struct ZyboUARTState *state);
-
-int zybo_uart_reset(struct UARTDriver *self) {
- // Ensure all required memory is allocated
- struct ZyboUARTState *state = self->state;
- if (state == NULL) return -1;
- if (state->inst == NULL) return -1;
- if (state->queue == NULL) return -1;
-
- XUartPs *inst = state->inst;
-
- // Configure XUartPs instance
- XUartPs_Config* config = XUartPs_LookupConfig(XPAR_PS7_UART_0_DEVICE_ID);
- if (XUartPs_CfgInitialize(inst, config, config->BaseAddress) != XST_SUCCESS) {
- return -1;
- }
-
- // Set UART Baudrate
- if(XUartPs_SetBaudRate_ours(inst, BAUD_RATE) != XST_SUCCESS) {
- return -1;
- }
-
- // Clear Tx/Rx FIFOs
- int* uart_ctrl_reg = (int*) inst->Config.BaseAddress;
- *uart_ctrl_reg |= 0x00000003; // clear TX & RX
-
- // Setup Interrupts
- if (SetupInterruptSystem(state, XPAR_PS7_UART_0_INTR, (Xil_ExceptionHandler) uart_interrupt_handler) != XST_SUCCESS) {
- return -1;
- }
-
- // Interrupts selected: Rx FIFO threashold reached, RX overflow, timeout
- u32 IntrMask = XUARTPS_IXR_RXFULL | XUARTPS_IXR_RXOVR | XUARTPS_IXR_TOUT;
- XUartPs_SetInterruptMask(inst, IntrMask);
-
- /*
- * Set the receiver timeout. If it is not set, and the last few bytes
- * of data do not trigger the over-water or full interrupt, the bytes
- * will not be received. By default it is disabled.
- * Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the
- * timeout function.
- *
- * The setting of 8 will timeout after 8 x 4 = 32 character times.
- * Increase the time out value if baud rate is high, decrease it if
- * baud rate is low.
- */
- XUartPs_SetRecvTimeout(inst, 8);
-
- // Second argument is the number of bytes to trigger an interrupt at
- XUartPs_SetFifoThreshold(inst, 48);
-
- return 0;
-}
-
-int zybo_uart_write(struct UARTDriver *self, unsigned char c) {
- struct ZyboUARTState *state = self->state;
- XUartPs *inst = state->inst;
- XUartPs_SendByte(inst->Config.BaseAddress, c);
- return 0;
-}
-
-int zybo_uart_read(struct UARTDriver *self, unsigned char *c) {
- struct ZyboUARTState *state = self->state;
- struct Queue *queue = state->queue;
- if (queue_remove(queue, c)) return -1;
- else return 0;
-}
-
-//This is copied from xuart driver
-/***************************************************/
-
-#define XUARTPS_MAX_BAUD_ERROR_RATE 3 /* max % error allowed */
-int XUartPs_SetBaudRate_ours(XUartPs *InstancePtr, u32 BaudRate)
-{
- u8 IterBAUDDIV; /* Iterator for available baud divisor values */
- u32 BRGR_Value; /* Calculated value for baud rate generator */
- u32 CalcBaudRate; /* Calculated baud rate */
- u32 BaudError; /* Diff between calculated and requested baud rate */
- u32 Best_BRGR = 0; /* Best value for baud rate generator */
- u8 Best_BAUDDIV = 0; /* Best value for baud divisor */
- u32 Best_Error = 0xFFFFFFFF;
- u32 PercentError;
- u32 ModeReg;
- u32 InputClk;
-
- /*
- * Asserts validate the input arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- //Xil_AssertNonvoid(BaudRate <= XUARTPS_MAX_RATE);
- Xil_AssertNonvoid(BaudRate >= XUARTPS_MIN_RATE);
-
- /*
- * Make sure the baud rate is not impossilby large.
- * Fastest possible baud rate is Input Clock / 2.
- */
- if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
- return XST_UART_BAUD_ERROR;
- }
- /*
- * Check whether the input clock is divided by 8
- */
- ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- InputClk = InstancePtr->Config.InputClockHz;
- if(ModeReg & XUARTPS_MR_CLKSEL) {
- InputClk = InstancePtr->Config.InputClockHz / 8;
- }
-
- /*
- * Determine the Baud divider. It can be 4to 254.
- * Loop through all possible combinations
- */
- for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
-
- /*
- * Calculate the value for BRGR register
- */
- BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
-
- /*
- * Calculate the baud rate from the BRGR value
- */
- CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
-
- /*
- * Avoid unsigned integer underflow
- */
- if (BaudRate > CalcBaudRate) {
- BaudError = BaudRate - CalcBaudRate;
- }
- else {
- BaudError = CalcBaudRate - BaudRate;
- }
-
- /*
- * Find the calculated baud rate closest to requested baud rate.
- */
- if (Best_Error > BaudError) {
-
- Best_BRGR = BRGR_Value;
- Best_BAUDDIV = IterBAUDDIV;
- Best_Error = BaudError;
- }
- }
-
- /*
- * Make sure the best error is not too large.
- */
- PercentError = (Best_Error * 100) / BaudRate;
- if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
- return XST_UART_BAUD_ERROR;
- }
-
- /*
- * Disable TX and RX to avoid glitches when setting the baud rate.
- */
- XUartPs_DisableUart(InstancePtr);
-
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
-
- /*
- * Enable device
- */
- XUartPs_EnableUart(InstancePtr);
-
- InstancePtr->BaudRate = BaudRate;
-
- return XST_SUCCESS;
-
-}
-
-void uart_interrupt_handler(struct ZyboUARTState *state) {
- u32 IsrStatus;
- XUartPs *InstancePtr = state->inst;
- struct Queue *queue = state->queue;
-
- /*
- * Read the interrupt ID register to determine which
- * interrupt is active
- */
- IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IMR_OFFSET);
-
- IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_ISR_OFFSET);
-
- /*
- * Read the Channel Status Register to determine if there is any data in
- * the RX FIFO
- */
-
- u32 CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_SR_OFFSET);
-
- while (0 == (CsrRegister & XUARTPS_SR_RXEMPTY)) {
- u8 byte = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, XUARTPS_FIFO_OFFSET);
- queue_add(queue, byte);
- CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, XUARTPS_SR_OFFSET);
- }
-
- // Clear the interrupt status.
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET,
- IsrStatus);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets up the interrupt system so interrupts can occur for the
-* Uart. This function is application-specific.
-*
-* @param IntcInstancePtr is a pointer to the instance of the INTC.
-* @param UartInstancePtr contains a pointer to the instance of the UART
-* driver which is going to be connected to the interrupt
-* controller.
-* @param UartIntrId is the interrupt Id and is typically
-* XPAR_<UARTPS_instance>_INTR value from xparameters.h.
-*
-* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
-*
-* @note None.
-*
-****************************************************************************/
-int SetupInterruptSystem(struct ZyboUARTState *state, u16 UartIntrId, Xil_ExceptionHandler handler)
-{
- int Status;
- XScuGic_Config *IntcConfig; /* Config for interrupt controller */
-
- /* Initialize the interrupt controller driver */
- IntcConfig = XScuGic_LookupConfig(XPAR_SCUGIC_SINGLE_DEVICE_ID);
- if (NULL == IntcConfig) {
- return XST_FAILURE;
- }
-
- memset(&state->xscugic, 0, sizeof(XScuGic));
- Status = XScuGic_CfgInitialize(&state->xscugic, IntcConfig,
- IntcConfig->CpuBaseAddress);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- /*
- * Connect the interrupt controller interrupt handler to the
- * hardware interrupt handling logic in the processor.
- */
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
- (Xil_ExceptionHandler) XScuGic_InterruptHandler,
- &state->xscugic);
-
- /*
- * Connect a device driver handler that will be called when an
- * interrupt for the device occurs, the device driver handler
- * performs the specific interrupt processing for the device
- */
- Status = XScuGic_Connect(&state->xscugic, UartIntrId,
- handler,
- (void *) state);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- /* Enable the interrupt for the device */
- XScuGic_Enable(&state->xscugic, UartIntrId);
-
- /* Enable interrupts */
- Xil_ExceptionEnable();
-
- return XST_SUCCESS;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/lscript.ld b/quad/xsdk_workspace_vivado/real_quad_fresh/src/lscript.ld
deleted file mode 100644
index a9e7524bb..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/lscript.ld
+++ /dev/null
@@ -1,284 +0,0 @@
-/*******************************************************************/
-/* */
-/* This file is automatically generated by linker script generator.*/
-/* */
-/* Version: Xilinx EDK 14.7 EDK_P.20131013 */
-/* */
-/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
-/* */
-/* Description : Cortex-A9 Linker Script */
-/* */
-/*******************************************************************/
-
-_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x100000;
-_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x6400000;
-
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-_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
-_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
-_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
-
-/* Define Memories in the system */
-
-MEMORY
-{
- ps7_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x00100000, LENGTH = 0x1FF00000
- ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000
- ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
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-
-/* Specify the default entry point to the program */
-
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-
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diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/main.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/main.c
deleted file mode 100644
index 716a876a9..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/main.c
+++ /dev/null
@@ -1,72 +0,0 @@
-#include <stdio.h>
-#include "hw_impl_zybo.h"
-#include "quad_app.h"
-#include "type_def.h"
-#include "platform.h"
-
-//#define RUN_TESTS
-
-/**
- * Create the hardware drivers, and place them on the hardware struct.
- *
- * Things to keep in mind:
- * - The CommDriver requires a UART. Hence, make the a UARTDriver first
- * and then give that instance to the CommDriver.
- * - Same for GPSDriver, except it needs a different hardware device.
- * - The I2C devices (IMU, LIDAR, Optical Flow), need a I2C bus. Hence
- * make a I2CDriver first, then give the appropariate instance the
- * device drivers.
- * - Currently, we are putting the Lidar on its own bus. Apparently,
- * when looking at an OScope with the Lidar on a bus with other
- * devices, it does not look right. The SCL line would never
- * go all the way back down to 0 volts
- */
-int setup_hardware(hardware_t *hardware) {
- hardware->rc_receiver = create_zybo_rc_receiver();
- hardware->motors = create_zybo_motors();
- hardware->uart_0 = create_zybo_uart(0);
- hardware->uart_1 = create_zybo_uart(1);
- hardware->comm = create_zybo_comm(&hardware->uart_0);
- hardware->gps = create_zybo_gps(&hardware->uart_1);
- hardware->global_timer = create_zybo_global_timer();
- //hardware->axi_timer = create_zybo_axi_timer();
- hardware->mio7_led = create_zybo_mio7_led();
- hardware->sys = create_zybo_system();
- hardware->i2c_0 = create_zybo_i2c(0);
- hardware->i2c_1 = create_zybo_i2c(1);
- hardware->imu = create_zybo_imu(&hardware->i2c_0);
- hardware->lidar = create_zybo_lidar(&hardware->i2c_1);
- hardware->of = create_zybo_optical_flow(&hardware->i2c_0);
- return 0;
-}
-
-int main()
-{
- // Zynq initialization
- init_platform();
-
-#ifdef RUN_TESTS
- //test_zybo_mio7_led_and_system();
- //test_zybo_i2c();
- //test_zybo_i2c_imu();
- test_zybo_i2c_px4flow();
- //test_zybo_i2c_lidar();
- //test_zybo_i2c_all();
- //test_zybo_rc_receiver();
- //test_zybo_motors();
- //test_zybo_uart();
- //test_zybo_axi_timer();
- //test_zybo_uart_comm();
- return 0;
-#endif
-
- // Run the main quad application
- quad_main(setup_hardware);
-
- while(1) {
- volatile int i = 0;
- i++;
- }
-
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform.c
deleted file mode 100644
index ea7849798..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-******************************************************************************/
-
-#include "xparameters.h"
-#include "xil_cache.h"
-
-#include "platform_config.h"
-
-/*
- * Uncomment the following line if ps7 init source files are added in the
- * source directory for compiling example outside of SDK.
- */
-/*#include "ps7_init.h"*/
-
-#ifdef STDOUT_IS_16550
- #include "xuartns550_l.h"
-
- #define UART_BAUD 9600
-#endif
-
-void
-enable_caches()
-{
-#ifdef __PPC__
- Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
- Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
-#elif __MICROBLAZE__
-#ifdef XPAR_MICROBLAZE_USE_ICACHE
- Xil_ICacheEnable();
-#endif
-#ifdef XPAR_MICROBLAZE_USE_DCACHE
- Xil_DCacheEnable();
-#endif
-#endif
-}
-
-void
-disable_caches()
-{
- Xil_DCacheDisable();
- Xil_ICacheDisable();
-}
-
-void
-init_uart()
-{
-#ifdef STDOUT_IS_16550
- XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
- XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
-#endif
-#ifdef STDOUT_IS_PS7_UART
- /* Bootrom/BSP configures PS7 UART to 115200 bps */
-#endif
-}
-
-void
-init_platform()
-{
- /*
- * If you want to run this example outside of SDK,
- * uncomment the following line and also #include "ps7_init.h" at the top.
- * Make sure that the ps7_init.c and ps7_init.h files are included
- * along with this example source files for compilation.
- */
- /* ps7_init();*/
- enable_caches();
- init_uart();
-}
-
-void
-cleanup_platform()
-{
- disable_caches();
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform.h b/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform.h
deleted file mode 100644
index efc90882b..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2008 Xilinx, Inc. All rights reserved.
- *
- * Xilinx, Inc.
- * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
- * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
- * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
- * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
- * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
- * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
- * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
- * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
- * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
- * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- */
-
-#ifndef __PLATFORM_H_
-#define __PLATFORM_H_
-
-#include "platform_config.h"
-
-void init_platform();
-void cleanup_platform();
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform_config.h b/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform_config.h
deleted file mode 100644
index c07ab1cba..000000000
--- a/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform_config.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __PLATFORM_CONFIG_H_
-#define __PLATFORM_CONFIG_H_
-
-#define STDOUT_IS_PS7_UART
-#define UART_DEVICE_ID 0
-#ifdef __PPC__
-#define CACHEABLE_REGION_MASK 0xf0000001
-#endif
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/recorder_test/.cproject b/quad/xsdk_workspace_vivado/recorder_test/.cproject
deleted file mode 100644
index e03e165f1..000000000
--- a/quad/xsdk_workspace_vivado/recorder_test/.cproject
+++ /dev/null
@@ -1,162 +0,0 @@
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- <project id="recorder_test.xilinx.gnu.armv7.exe.174313142" name="Xilinx ARM v7 Executable" projectType="xilinx.gnu.armv7.exe"/>
- </storageModule>
- <storageModule moduleId="scannerConfiguration">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.debug.2034508604;xilinx.gnu.armv7.exe.debug.2034508604.;xilinx.gnu.armv7.c.toolchain.compiler.debug.1587818788;xilinx.gnu.armv7.c.compiler.input.711971084">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
- </scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.release.1066765704;xilinx.gnu.armv7.exe.release.1066765704.">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
- </scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.release.1066765704;xilinx.gnu.armv7.exe.release.1066765704.;xilinx.gnu.armv7.c.toolchain.compiler.release.1685442427;xilinx.gnu.armv7.c.compiler.input.1616205127">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
- </scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.debug.2034508604;xilinx.gnu.armv7.exe.debug.2034508604.">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
- </scannerConfigBuildInfo>
- </storageModule>
-</cproject>
diff --git a/quad/xsdk_workspace_vivado/recorder_test/.gitignore b/quad/xsdk_workspace_vivado/recorder_test/.gitignore
deleted file mode 100644
index 3df573fe6..000000000
--- a/quad/xsdk_workspace_vivado/recorder_test/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/quad/xsdk_workspace_vivado/recorder_test/.project b/quad/xsdk_workspace_vivado/recorder_test/.project
deleted file mode 100644
index 10edf8bc7..000000000
--- a/quad/xsdk_workspace_vivado/recorder_test/.project
+++ /dev/null
@@ -1,26 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
- <name>recorder_test</name>
- <comment>Created by SDK v2018.2. recorder_test_bsp - ps7_cortexa9_0</comment>
- <projects>
- <project>recorder_test_bsp</project>
- </projects>
- <buildSpec>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
- <arguments>
- </arguments>
- </buildCommand>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
- <triggers>full,incremental,</triggers>
- <arguments>
- </arguments>
- </buildCommand>
- </buildSpec>
- <natures>
- <nature>org.eclipse.cdt.core.cnature</nature>
- <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
- <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
- </natures>
-</projectDescription>
diff --git a/quad/xsdk_workspace_vivado/recorder_test/src/helloworld.c b/quad/xsdk_workspace_vivado/recorder_test/src/helloworld.c
deleted file mode 100644
index 879c4edd4..000000000
--- a/quad/xsdk_workspace_vivado/recorder_test/src/helloworld.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/*
- * helloworld.c: simple test application
- *
- * This application configures UART 16550 to baud rate 9600.
- * PS7 UART (Zynq) is not initialized by this application, since
- * bootrom/bsp configures it to baud rate 115200
- *
- * ------------------------------------------------
- * | UART TYPE BAUD RATE |
- * ------------------------------------------------
- * uartns550 9600
- * uartlite Configurable only in HW design
- * ps7_uart 115200 (configured by bootrom/bsp)
- */
-
-#include <stdio.h>
-#include "platform.h"
-#include "xil_printf.h"
-
-
-int main()
-{
- init_platform();
-
- print("Hello World\n\r");
-
- while(1) {
- xil_printf("Hello World 0: %10d %10d\r", *(volatile int*)(0x43C00000), *(volatile int*)(0x43C00004));
- }
-
- cleanup_platform();
- return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/recorder_test/src/lscript.ld b/quad/xsdk_workspace_vivado/recorder_test/src/lscript.ld
deleted file mode 100644
index fe0de6cb7..000000000
--- a/quad/xsdk_workspace_vivado/recorder_test/src/lscript.ld
+++ /dev/null
@@ -1,288 +0,0 @@
-/*******************************************************************/
-/* */
-/* This file is automatically generated by linker script generator.*/
-/* */
-/* Version: */
-/* */
-/* Copyright (c) 2010-2016 Xilinx, Inc. All rights reserved. */
-/* */
-/* Description : Cortex-A9 Linker Script */
-/* */
-/*******************************************************************/
-
-_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
-_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
-
-_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
-_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
-_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
-_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
-_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
-
-/* Define Memories in the system */
-
-MEMORY
-{
- ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3FF00000
- ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000
- ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
- ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
-}
-
-/* Specify the default entry point to the program */
-
-ENTRY(_vector_table)
-
-/* Define the sections, and where they are mapped in memory */
-
-SECTIONS
-{
-.text : {
- KEEP (*(.vectors))
- *(.boot)
- *(.text)
- *(.text.*)
- *(.gnu.linkonce.t.*)
- *(.plt)
- *(.gnu_warning)
- *(.gcc_execpt_table)
- *(.glue_7)
- *(.glue_7t)
- *(.vfp11_veneer)
- *(.ARM.extab)
- *(.gnu.linkonce.armextab.*)
-} > ps7_ddr_0
-
-.init : {
- KEEP (*(.init))
-} > ps7_ddr_0
-
-.fini : {
- KEEP (*(.fini))
-} > ps7_ddr_0
-
-.rodata : {
- __rodata_start = .;
- *(.rodata)
- *(.rodata.*)
- *(.gnu.linkonce.r.*)
- __rodata_end = .;
-} > ps7_ddr_0
-
-.rodata1 : {
- __rodata1_start = .;
- *(.rodata1)
- *(.rodata1.*)
- __rodata1_end = .;
-} > ps7_ddr_0
-
-.sdata2 : {
- __sdata2_start = .;
- *(.sdata2)
- *(.sdata2.*)
- *(.gnu.linkonce.s2.*)
- __sdata2_end = .;
-} > ps7_ddr_0
-
-.sbss2 : {
- __sbss2_start = .;
- *(.sbss2)
- *(.sbss2.*)
- *(.gnu.linkonce.sb2.*)
- __sbss2_end = .;
-} > ps7_ddr_0
-
-.data : {
- __data_start = .;
- *(.data)
- *(.data.*)
- *(.gnu.linkonce.d.*)
- *(.jcr)
- *(.got)
- *(.got.plt)
- __data_end = .;
-} > ps7_ddr_0
-
-.data1 : {
- __data1_start = .;
- *(.data1)
- *(.data1.*)
- __data1_end = .;
-} > ps7_ddr_0
-
-.got : {
- *(.got)
-} > ps7_ddr_0
-
-.ctors : {
- __CTOR_LIST__ = .;
- ___CTORS_LIST___ = .;
- KEEP (*crtbegin.o(.ctors))
- KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- __CTOR_END__ = .;
- ___CTORS_END___ = .;
-} > ps7_ddr_0
-
-.dtors : {
- __DTOR_LIST__ = .;
- ___DTORS_LIST___ = .;
- KEEP (*crtbegin.o(.dtors))
- KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- __DTOR_END__ = .;
- ___DTORS_END___ = .;
-} > ps7_ddr_0
-
-.fixup : {
- __fixup_start = .;
- *(.fixup)
- __fixup_end = .;
-} > ps7_ddr_0
-
-.eh_frame : {
- *(.eh_frame)
-} > ps7_ddr_0
-
-.eh_framehdr : {
- __eh_framehdr_start = .;
- *(.eh_framehdr)
- __eh_framehdr_end = .;
-} > ps7_ddr_0
-
-.gcc_except_table : {
- *(.gcc_except_table)
-} > ps7_ddr_0
-
-.mmu_tbl (ALIGN(16384)) : {
- __mmu_tbl_start = .;
- *(.mmu_tbl)
- __mmu_tbl_end = .;
-} > ps7_ddr_0
-
-.ARM.exidx : {
- __exidx_start = .;
- *(.ARM.exidx*)
- *(.gnu.linkonce.armexidix.*.*)
- __exidx_end = .;
-} > ps7_ddr_0
-
-.preinit_array : {
- __preinit_array_start = .;
- KEEP (*(SORT(.preinit_array.*)))
- KEEP (*(.preinit_array))
- __preinit_array_end = .;
-} > ps7_ddr_0
-
-.init_array : {
- __init_array_start = .;
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array))
- __init_array_end = .;
-} > ps7_ddr_0
-
-.fini_array : {
- __fini_array_start = .;
- KEEP (*(SORT(.fini_array.*)))
- KEEP (*(.fini_array))
- __fini_array_end = .;
-} > ps7_ddr_0
-
-.ARM.attributes : {
- __ARM.attributes_start = .;
- *(.ARM.attributes)
- __ARM.attributes_end = .;
-} > ps7_ddr_0
-
-.sdata : {
- __sdata_start = .;
- *(.sdata)
- *(.sdata.*)
- *(.gnu.linkonce.s.*)
- __sdata_end = .;
-} > ps7_ddr_0
-
-.sbss (NOLOAD) : {
- __sbss_start = .;
- *(.sbss)
- *(.sbss.*)
- *(.gnu.linkonce.sb.*)
- __sbss_end = .;
-} > ps7_ddr_0
-
-.tdata : {
- __tdata_start = .;
- *(.tdata)
- *(.tdata.*)
- *(.gnu.linkonce.td.*)
- __tdata_end = .;
-} > ps7_ddr_0
-
-.tbss : {
- __tbss_start = .;
- *(.tbss)
- *(.tbss.*)
- *(.gnu.linkonce.tb.*)
- __tbss_end = .;
-} > ps7_ddr_0
-
-.bss (NOLOAD) : {
- __bss_start = .;
- *(.bss)
- *(.bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- __bss_end = .;
-} > ps7_ddr_0
-
-_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
-
-_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
-
-/* Generate Stack and Heap definitions */
-
-.heap (NOLOAD) : {
- . = ALIGN(16);
- _heap = .;
- HeapBase = .;
- _heap_start = .;
- . += _HEAP_SIZE;
- _heap_end = .;
- HeapLimit = .;
-} > ps7_ddr_0
-
-.stack (NOLOAD) : {
- . = ALIGN(16);
- _stack_end = .;
- . += _STACK_SIZE;
- . = ALIGN(16);
- _stack = .;
- __stack = _stack;
- . = ALIGN(16);
- _irq_stack_end = .;
- . += _IRQ_STACK_SIZE;
- . = ALIGN(16);
- __irq_stack = .;
- _supervisor_stack_end = .;
- . += _SUPERVISOR_STACK_SIZE;
- . = ALIGN(16);
- __supervisor_stack = .;
- _abort_stack_end = .;
- . += _ABORT_STACK_SIZE;
- . = ALIGN(16);
- __abort_stack = .;
- _fiq_stack_end = .;
- . += _FIQ_STACK_SIZE;
- . = ALIGN(16);
- __fiq_stack = .;
- _undef_stack_end = .;
- . += _UNDEF_STACK_SIZE;
- . = ALIGN(16);
- __undef_stack = .;
-} > ps7_ddr_0
-
-_end = .;
-}
-
diff --git a/quad/xsdk_workspace_vivado/recorder_test/src/platform.c b/quad/xsdk_workspace_vivado/recorder_test/src/platform.c
deleted file mode 100644
index 0ee2dcbaf..000000000
--- a/quad/xsdk_workspace_vivado/recorder_test/src/platform.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include "xparameters.h"
-#include "xil_cache.h"
-
-#include "platform_config.h"
-
-/*
- * Uncomment one of the following two lines, depending on the target,
- * if ps7/psu init source files are added in the source directory for
- * compiling example outside of SDK.
- */
-/*#include "ps7_init.h"*/
-/*#include "psu_init.h"*/
-
-#ifdef STDOUT_IS_16550
- #include "xuartns550_l.h"
-
- #define UART_BAUD 9600
-#endif
-
-void
-enable_caches()
-{
-#ifdef __PPC__
- Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
- Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
-#elif __MICROBLAZE__
-#ifdef XPAR_MICROBLAZE_USE_ICACHE
- Xil_ICacheEnable();
-#endif
-#ifdef XPAR_MICROBLAZE_USE_DCACHE
- Xil_DCacheEnable();
-#endif
-#endif
-}
-
-void
-disable_caches()
-{
-#ifdef __MICROBLAZE__
-#ifdef XPAR_MICROBLAZE_USE_DCACHE
- Xil_DCacheDisable();
-#endif
-#ifdef XPAR_MICROBLAZE_USE_ICACHE
- Xil_ICacheDisable();
-#endif
-#endif
-}
-
-void
-init_uart()
-{
-#ifdef STDOUT_IS_16550
- XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
- XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
-#endif
- /* Bootrom/BSP configures PS7/PSU UART to 115200 bps */
-}
-
-void
-init_platform()
-{
- /*
- * If you want to run this example outside of SDK,
- * uncomment one of the following two lines and also #include "ps7_init.h"
- * or #include "ps7_init.h" at the top, depending on the target.
- * Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included
- * along with this example source files for compilation.
- */
- /* ps7_init();*/
- /* psu_init();*/
- enable_caches();
- init_uart();
-}
-
-void
-cleanup_platform()
-{
- disable_caches();
-}
diff --git a/quad/xsdk_workspace_vivado/recorder_test/src/platform.h b/quad/xsdk_workspace_vivado/recorder_test/src/platform.h
deleted file mode 100644
index e273e3718..000000000
--- a/quad/xsdk_workspace_vivado/recorder_test/src/platform.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#ifndef __PLATFORM_H_
-#define __PLATFORM_H_
-
-#include "platform_config.h"
-
-void init_platform();
-void cleanup_platform();
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/recorder_test/src/platform_config.h b/quad/xsdk_workspace_vivado/recorder_test/src/platform_config.h
deleted file mode 100644
index eda2e2eba..000000000
--- a/quad/xsdk_workspace_vivado/recorder_test/src/platform_config.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __PLATFORM_CONFIG_H_
-#define __PLATFORM_CONFIG_H_
-
-#define STDOUT_IS_PS7_UART
-#define UART_DEVICE_ID 0
-#endif
diff --git a/quad/xsdk_workspace_vivado/recorder_test_bsp/.cproject b/quad/xsdk_workspace_vivado/recorder_test_bsp/.cproject
deleted file mode 100644
index 519033057..000000000
--- a/quad/xsdk_workspace_vivado/recorder_test_bsp/.cproject
+++ /dev/null
@@ -1,13 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
- <storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="org.eclipse.cdt.core.default.config.37663476">
- <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.37663476" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
- <externalSettings/>
- <extensions/>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
- </cconfiguration>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
-</cproject>
diff --git a/quad/xsdk_workspace_vivado/recorder_test_bsp/.project b/quad/xsdk_workspace_vivado/recorder_test_bsp/.project
deleted file mode 100644
index c0fd0d66b..000000000
--- a/quad/xsdk_workspace_vivado/recorder_test_bsp/.project
+++ /dev/null
@@ -1,75 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
- <name>recorder_test_bsp</name>
- <comment>Created by SDK v2018.2</comment>
- <projects>
- </projects>
- <buildSpec>
- <buildCommand>
- <name>org.eclipse.cdt.make.core.makeBuilder</name>
- <arguments>
- <dictionary>
- <key>org.eclipse.cdt.core.errorOutputParser</key>
- <value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.append_environment</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.arguments</key>
- <value></value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.command</key>
- <value>make</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.target.auto</key>
- <value>all</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.target.clean</key>
- <value>clean</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.target.inc</key>
- <value>all</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.enableAutoBuild</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.enableCleanBuild</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.enableFullBuild</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.environment</key>
- <value></value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.stopOnError</key>
- <value>false</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
- <value>true</value>
- </dictionary>
- </arguments>
- </buildCommand>
- </buildSpec>
- <natures>
- <nature>com.xilinx.sdk.sw.SwProjectNature</nature>
- <nature>org.eclipse.cdt.core.cnature</nature>
- <nature>org.eclipse.cdt.make.core.makeNature</nature>
- </natures>
-</projectDescription>
diff --git a/quad/xsdk_workspace_vivado/recorder_test_bsp/.sdkproject b/quad/xsdk_workspace_vivado/recorder_test_bsp/.sdkproject
deleted file mode 100644
index dd82e57dd..000000000
--- a/quad/xsdk_workspace_vivado/recorder_test_bsp/.sdkproject
+++ /dev/null
@@ -1,4 +0,0 @@
-THIRPARTY=false
-HW_PROJECT_REFERENCE=design_1_wrapper_hw_platform_0
-PROCESSOR=ps7_cortexa9_0
-MSS_FILE=system.mss
diff --git a/quad/xsdk_workspace_vivado/recorder_test_bsp/Makefile b/quad/xsdk_workspace_vivado/recorder_test_bsp/Makefile
deleted file mode 100644
index 1e68922ca..000000000
--- a/quad/xsdk_workspace_vivado/recorder_test_bsp/Makefile
+++ /dev/null
@@ -1,35 +0,0 @@
-# Makefile generated by Xilinx.
-
-PROCESSOR = ps7_cortexa9_0
-LIBRARIES = ${PROCESSOR}/lib/libxil.a
-BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
-SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
-
-ifneq (,$(findstring win,$(RDI_PLATFORM)))
- SHELL = CMD
-endif
-
-all: libs
- @echo 'Finished building libraries'
-
-include: $(addsuffix /make.include,$(SUBDIRS))
-
-libs: $(addsuffix /make.libs,$(SUBDIRS))
-
-clean: $(addsuffix /make.clean,$(SUBDIRS))
-
-$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
- cp -f $< $@
-
-%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
- @echo "Running Make include in $(subst /make.include,,$@)"
- $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
-
-%/make.libs: include
- @echo "Running Make libs in $(subst /make.libs,,$@)"
- $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
-
-%/make.clean:
- $(MAKE) -C $(subst /make.clean,,$@) -s clean
-clean:
- rm -f ${PROCESSOR}/lib/libxil.a
diff --git a/quad/xsdk_workspace_vivado/recorder_test_bsp/system.mss b/quad/xsdk_workspace_vivado/recorder_test_bsp/system.mss
deleted file mode 100644
index f51b5f562..000000000
--- a/quad/xsdk_workspace_vivado/recorder_test_bsp/system.mss
+++ /dev/null
@@ -1,249 +0,0 @@
-
- PARAMETER VERSION = 2.2.0
-
-
-BEGIN OS
- PARAMETER OS_NAME = standalone
- PARAMETER OS_VER = 6.7
- PARAMETER PROC_INSTANCE = ps7_cortexa9_0
- PARAMETER stdin = ps7_uart_1
- PARAMETER stdout = ps7_uart_1
-END
-
-
-BEGIN PROCESSOR
- PARAMETER DRIVER_NAME = cpu_cortexa9
- PARAMETER DRIVER_VER = 2.6
- PARAMETER HW_INSTANCE = ps7_cortexa9_0
-END
-
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = gpio
- PARAMETER DRIVER_VER = 4.3
- PARAMETER HW_INSTANCE = axi_gpio_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = gpio
- PARAMETER DRIVER_VER = 4.3
- PARAMETER HW_INSTANCE = axi_gpio_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = gpio
- PARAMETER DRIVER_VER = 4.3
- PARAMETER HW_INSTANCE = axi_gpio_2
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = gpio
- PARAMETER DRIVER_VER = 4.3
- PARAMETER HW_INSTANCE = axi_gpio_3
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_afi_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_afi_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_afi_2
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_afi_3
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = coresightps_dcc
- PARAMETER DRIVER_VER = 1.4
- PARAMETER HW_INSTANCE = ps7_coresight_comp_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = ddrps
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = ps7_ddr_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_ddrc_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = devcfg
- PARAMETER DRIVER_VER = 3.5
- PARAMETER HW_INSTANCE = ps7_dev_cfg_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = dmaps
- PARAMETER DRIVER_VER = 2.3
- PARAMETER HW_INSTANCE = ps7_dma_ns
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = dmaps
- PARAMETER DRIVER_VER = 2.3
- PARAMETER HW_INSTANCE = ps7_dma_s
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = emacps
- PARAMETER DRIVER_VER = 3.7
- PARAMETER HW_INSTANCE = ps7_ethernet_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_globaltimer_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = gpiops
- PARAMETER DRIVER_VER = 3.3
- PARAMETER HW_INSTANCE = ps7_gpio_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_gpv_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_intc_dist_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_iop_bus_config_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_l2cachec_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_ocmc_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_pl310_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_pmu_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = qspips
- PARAMETER DRIVER_VER = 3.4
- PARAMETER HW_INSTANCE = ps7_qspi_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_qspi_linear_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_ram_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_ram_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_scuc_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = scugic
- PARAMETER DRIVER_VER = 3.9
- PARAMETER HW_INSTANCE = ps7_scugic_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = scutimer
- PARAMETER DRIVER_VER = 2.1
- PARAMETER HW_INSTANCE = ps7_scutimer_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = scuwdt
- PARAMETER DRIVER_VER = 2.1
- PARAMETER HW_INSTANCE = ps7_scuwdt_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = sdps
- PARAMETER DRIVER_VER = 3.5
- PARAMETER HW_INSTANCE = ps7_sd_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_slcr_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 3.6
- PARAMETER HW_INSTANCE = ps7_uart_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = usbps
- PARAMETER DRIVER_VER = 2.4
- PARAMETER HW_INSTANCE = ps7_usb_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = xadcps
- PARAMETER DRIVER_VER = 2.2
- PARAMETER HW_INSTANCE = ps7_xadc_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_recorder
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_recorder_0
-END
-
-
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/.cproject b/quad/xsdk_workspace_vivado/standalone_bsp_0/.cproject
deleted file mode 100644
index 00ffbf876..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/.cproject
+++ /dev/null
@@ -1,13 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
- <storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="org.eclipse.cdt.core.default.config.1030668811">
- <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1030668811" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
- <externalSettings/>
- <extensions/>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
- </cconfiguration>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
-</cproject>
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/.project b/quad/xsdk_workspace_vivado/standalone_bsp_0/.project
deleted file mode 100644
index cf86d526d..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/.project
+++ /dev/null
@@ -1,75 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
- <name>standalone_bsp_0</name>
- <comment>Created by SDK v2017.1</comment>
- <projects>
- </projects>
- <buildSpec>
- <buildCommand>
- <name>org.eclipse.cdt.make.core.makeBuilder</name>
- <arguments>
- <dictionary>
- <key>org.eclipse.cdt.core.errorOutputParser</key>
- <value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.append_environment</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.arguments</key>
- <value></value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.command</key>
- <value>make</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.target.auto</key>
- <value>all</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.target.clean</key>
- <value>clean</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.build.target.inc</key>
- <value>all</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.enableAutoBuild</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.enableCleanBuild</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.enableFullBuild</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>
- <value>true</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.environment</key>
- <value></value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.stopOnError</key>
- <value>false</value>
- </dictionary>
- <dictionary>
- <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
- <value>true</value>
- </dictionary>
- </arguments>
- </buildCommand>
- </buildSpec>
- <natures>
- <nature>com.xilinx.sdk.sw.SwProjectNature</nature>
- <nature>org.eclipse.cdt.core.cnature</nature>
- <nature>org.eclipse.cdt.make.core.makeNature</nature>
- </natures>
-</projectDescription>
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/.sdkproject b/quad/xsdk_workspace_vivado/standalone_bsp_0/.sdkproject
deleted file mode 100644
index 6e301ca60..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/.sdkproject
+++ /dev/null
@@ -1,4 +0,0 @@
-THIRPARTY=false
-HW_PROJECT_REFERENCE=quad_wrapper_hw_platform_0
-PROCESSOR=ps7_cortexa9_0
-MSS_FILE=system.mss
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/Makefile
deleted file mode 100644
index 1ace345f6..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/Makefile
+++ /dev/null
@@ -1,35 +0,0 @@
-# Makefile generated by Xilinx.
-
-PROCESSOR = ps7_cortexa9_0
-LIBRARIES = ${PROCESSOR}/lib/libxil.a
-BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
-SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
-
-ifneq (,$(findstring win,$(RDI_PLATFORM)))
- SHELL = CMD
-endif
-
-all: libs
- @echo 'Finished building libraries'
-
-include: $(addsuffix /make.include,$(SUBDIRS))
-
-libs: $(addsuffix /make.libs,$(SUBDIRS))
-
-clean: $(addsuffix /make.clean,$(SUBDIRS))
-
-$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
- cp -f $< $@
-
-%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
- @echo "Running Make include in $(subst /make.include,,$@)"
- $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -Wall -Wextra"
-
-%/make.libs: include
- @echo "Running Make libs in $(subst /make.libs,,$@)"
- $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -Wall -Wextra"
-
-%/make.clean:
- $(MAKE) -C $(subst /make.clean,,$@) -s clean
-clean:
- rm -f ${PROCESSOR}/lib/libxil.a
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/sleep.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/sleep.h
deleted file mode 100644
index 27add6605..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/sleep.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#ifndef SLEEP_H
-#define SLEEP_H
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-int usleep(unsigned long useconds);
-unsigned sleep(unsigned int seconds);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xttcps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xttcps.h
deleted file mode 100644
index bae9d28fe..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xttcps.h
+++ /dev/null
@@ -1,466 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xttcps.h
-* @addtogroup ttcps_v3_0
-* @{
-* @details
-*
-* This is the driver for one 16-bit timer counter in the Triple Timer Counter
-* (TTC) module in the Ps block.
-*
-* The TTC module provides three independent timer/counter modules that can each
-* be clocked using either the system clock (pclk) or an externally driven
-* clock (ext_clk). In addition, each counter can independently prescale its
-* selected clock input (divided by 2 to 65536). Counters can be set to
-* decrement or increment.
-*
-* Each of the counters can be programmed to generate interrupt pulses:
-* . At a regular, predefined period, that is on a timed interval
-* . When the counter registers overflow
-* . When the count matches any one of the three 'match' registers
-*
-* Therefore, up to six different events can trigger a timer interrupt: three
-* match interrupts, an overflow interrupt, an interval interrupt and an event
-* timer interrupt. Note that the overflow interrupt and the interval interrupt
-* are mutually exclusive.
-*
-* <b>Initialization & Configuration</b>
-*
-* An XTtcPs_Config structure is used to configure a driver instance.
-* Information in the XTtcPs_Config structure is the hardware properties
-* about the device.
-*
-* A driver instance is initialized through
-* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
-* is a pointer to the XTtcPs_Config structure, it can be looked up statically
-* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
-* EffectiveAddr can be the static base address of the device or virtual
-* mapped address if address translation is supported.
-*
-* <b>Interrupts</b>
-*
-* Interrupt handler is not provided by the driver, as handling of interrupt
-* is application specific.
-*
-* @note
-* The default setting for a timer/counter is:
-* - Overflow Mode
-* - Internal clock (pclk) selected
-* - Counter disabled
-* - All Interrupts disabled
-* - Output waveforms disabled
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------------
-* 1.00a drg/jz 01/20/10 First release..
-* 2.0 adk 12/10/13 Updated as per the New Tcl API's
-* 3.0 pkp 12/09/14 Added support for Zynq Ultrascale Mp.Also code
-* modified for MISRA-C:2012 compliance.
-* 3.2 mus 10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
-* macros to return 32 bit values for zynq ultrascale+mpsoc
-* ms 01/23/17 Modified xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTTCPS_H /* prevent circular inclusions */
-#define XTTCPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xttcps_hw.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-/*
- * Flag for a9 processor
- */
- #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
- #define ARMA9
- #endif
-
-/*
- * Maximum Value for interval counter
- */
- #if defined(ARMA9)
- #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU
- #else
- #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU
- #endif
-
-/** @name Configuration options
- *
- * Options for the device. Each of the options is bit field, so more than one
- * options can be specified.
- *
- * @{
- */
-#define XTTCPS_OPTION_EXTERNAL_CLK 0x00000001U /**< External clock source */
-#define XTTCPS_OPTION_CLK_EDGE_NEG 0x00000002U /**< Clock on trailing edge for
- external clock*/
-#define XTTCPS_OPTION_INTERVAL_MODE 0x00000004U /**< Interval mode */
-#define XTTCPS_OPTION_DECREMENT 0x00000008U /**< Decrement the counter */
-#define XTTCPS_OPTION_MATCH_MODE 0x00000010U /**< Match mode */
-#define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U /**< No waveform output */
-#define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U /**< Waveform polarity */
-/*@}*/
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID for device */
- u32 BaseAddress; /**< Base address for device */
- u32 InputClockHz; /**< Input clock frequency */
-} XTtcPs_Config;
-
-/**
- * The XTtcPs driver instance data. The user is required to allocate a
- * variable of this type for each PS timer/counter device in the system. A
- * pointer to a variable of this type is then passed to various driver API
- * functions.
- */
-typedef struct {
- XTtcPs_Config Config; /**< Configuration structure */
- u32 IsReady; /**< Device is initialized and ready */
-} XTtcPs;
-
-/**
- * This typedef contains interval count
- */
-#if defined(ARMA9)
-typedef u16 XInterval;
-#else
-typedef u32 XInterval;
-#endif
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*
- * Internal helper macros
- */
-#define InstReadReg(InstancePtr, RegOffset) \
- (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
-
-#define InstWriteReg(InstancePtr, RegOffset, Data) \
- (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
-
-/*****************************************************************************/
-/**
-*
-* This function starts the counter/timer without resetting the counter value.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return None
-*
-* @note C-style signature:
-* void XTtcPs_Start(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#define XTtcPs_Start(InstancePtr) \
- InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
- (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
- ~XTTCPS_CNT_CNTRL_DIS_MASK))
-
-/*****************************************************************************/
-/**
-*
-* This function stops the counter/timer. This macro may be called at any time
-* to stop the counter. The counter holds the last value until it is reset,
-* restarted or enabled.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return None
-*
-* @note C-style signature:
-* void XTtcPs_Stop(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#define XTtcPs_Stop(InstancePtr) \
- InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
- (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
- XTTCPS_CNT_CNTRL_DIS_MASK))
-
-/*****************************************************************************/
-/**
-*
-* This function checks whether the timer counter has already started.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance
-*
-* @return Non-zero if the device has started, '0' otherwise.
-*
-* @note C-style signature:
-* int XTtcPs_IsStarted(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#define XTtcPs_IsStarted(InstancePtr) \
- ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
- XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
-
-/*****************************************************************************/
-/**
-*
-* This function returns the current 16-bit counter value. It may be called at
-* any time.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return zynq:16 bit counter value.
-* zynq ultrascale+mpsoc:32 bit counter value.
-*
-* @note C-style signature:
-* zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
-* zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#if defined(ARMA9)
-/*
- * ttc supports 16 bit counter for zynq
- */
-#define XTtcPs_GetCounterValue(InstancePtr) \
- (u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
-#else
-/*
- * ttc supports 32 bit counter for zynq ultrascale+mpsoc
- */
-#define XTtcPs_GetCounterValue(InstancePtr) \
- InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This function sets the interval value to be used in interval mode.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-* @param Value is the 16-bit value to be set in the interval register.
-*
-* @return None
-*
-* @note C-style signature:
-* void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value)
-*
-****************************************************************************/
-#define XTtcPs_SetInterval(InstancePtr, Value) \
- InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
-
-/*****************************************************************************/
-/**
-*
-* This function gets the interval value from the interval register.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return zynq:16 bit interval value.
-* zynq ultrascale+mpsoc:32 bit interval value.
-*
-* @note C-style signature:
-* zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
-* zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#if defined(ARMA9)
-/*
- * ttc supports 16 bit interval counter for zynq
- */
-#define XTtcPs_GetInterval(InstancePtr) \
- (u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
-#else
-/*
- * ttc supports 32 bit interval counter for zynq ultrascale+mpsoc
- */
-#define XTtcPs_GetInterval(InstancePtr) \
- InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
-#endif
-/*****************************************************************************/
-/**
-*
-* This macro resets the count register. It may be called at any time. The
-* counter is reset to either 0 or 0xFFFF, or the interval value, depending on
-* the increment/decrement mode. The state of the counter, as started or
-* stopped, is not affected by calling reset.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return None
-*
-* @note C-style signature:
-* void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#define XTtcPs_ResetCounterValue(InstancePtr) \
- InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
- (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
- (u32)XTTCPS_CNT_CNTRL_RST_MASK))
-
-/*****************************************************************************/
-/**
-*
-* This function enables the interrupts.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-* @param InterruptMask defines which interrupt should be enabled.
-* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
-* This is a bit mask, all set bits will be enabled, cleared bits
-* will not be disabled.
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
-*
-******************************************************************************/
-#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask) \
- InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
- (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) | \
- (InterruptMask)))
-
-/*****************************************************************************/
-/**
-*
-* This function disables the interrupts.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-* @param InterruptMask defines which interrupt should be disabled.
-* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
-* This is a bit mask, all set bits will be disabled, cleared bits
-* will not be disabled.
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
-*
-******************************************************************************/
-#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
- InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
- (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) & \
- ~(InterruptMask)))
-
-/*****************************************************************************/
-/**
-*
-* This function reads the interrupt status.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
-*
-******************************************************************************/
-#define XTtcPs_GetInterruptStatus(InstancePtr) \
- InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
-
-/*****************************************************************************/
-/**
-*
-* This function clears the interrupt status.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-* @param InterruptMask defines which interrupt should be cleared.
-* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
-* This is a bit mask, all set bits will be cleared, cleared bits
-* will not be cleared.
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
-*
-******************************************************************************/
-#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
- InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \
- (InterruptMask))
-
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Initialization functions in xttcps_sinit.c
- */
-XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
-
-/*
- * Required functions, in xttcps.c
- */
-s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
- XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
-
-void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value);
-u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
-
-void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
-u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
-
-void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
- XInterval *Interval, u8 *Prescaler);
-
-/*
- * Functions for options, in file xttcps_options.c
- */
-s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
-u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
-
-/*
- * Function for self-test, in file xttcps_selftest.c
- */
-s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xttcps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xttcps_hw.h
deleted file mode 100644
index af78bcd67..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xttcps_hw.h
+++ /dev/null
@@ -1,212 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xttcps_hw.h
-* @addtogroup ttcps_v3_0
-* @{
-*
-* This file defines the hardware interface to one of the three timer counters
-* in the Ps block.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -------------------------------------------------
-* 1.00a drg/jz 01/21/10 First release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTTCPS_HW_H /* prevent circular inclusions */
-#define XTTCPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of the device.
- *
- * @{
- */
-#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U /**< Clock Control Register */
-#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU /**< Counter Control Register*/
-#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U /**< Current Counter Value */
-#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U /**< Interval Count Value */
-#define XTTCPS_MATCH_0_OFFSET 0x00000030U /**< Match 1 value */
-#define XTTCPS_MATCH_1_OFFSET 0x0000003CU /**< Match 2 value */
-#define XTTCPS_MATCH_2_OFFSET 0x00000048U /**< Match 3 value */
-#define XTTCPS_ISR_OFFSET 0x00000054U /**< Interrupt Status Register */
-#define XTTCPS_IER_OFFSET 0x00000060U /**< Interrupt Enable Register */
-/* @} */
-
-/** @name Clock Control Register
- * Clock Control Register definitions
- * @{
- */
-#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U /**< Prescale enable */
-#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU /**< Prescale value */
-#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U /**< Prescale shift */
-#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U /**< Prescale disable */
-#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U /**< Clock source */
-#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U /**< External Clock edge */
-/* @} */
-
-/** @name Counter Control Register
- * Counter Control Register definitions
- * @{
- */
-#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U /**< Disable the counter */
-#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U /**< Interval mode */
-#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U /**< Decrement mode */
-#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U /**< Match mode */
-#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U /**< Reset counter */
-#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U /**< Enable waveform */
-#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U /**< Waveform polarity */
-#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U /**< Reset value */
-/* @} */
-
-/** @name Current Counter Value Register
- * Current Counter Value Register definitions
- * @{
- */
-#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU /**< 16-bit counter value */
-/* @} */
-
-/** @name Interval Value Register
- * Interval Value Register is the maximum value the counter will count up or
- * down to.
- * @{
- */
-#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU /**< 16-bit Interval value*/
-/* @} */
-
-/** @name Match Registers
- * Definitions for Match registers, each timer counter has three match
- * registers.
- * @{
- */
-#define XTTCPS_MATCH_MASK 0x0000FFFFU /**< 16-bit Match value */
-#define XTTCPS_NUM_MATCH_REG 3U /**< Num of Match reg */
-/* @} */
-
-/** @name Interrupt Registers
- * Following register bit mask is for all interrupt registers.
- *
- * @{
- */
-#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U /**< Interval Interrupt */
-#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U /**< Match 1 Interrupt */
-#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U /**< Match 2 Interrupt */
-#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U /**< Match 3 Interrupt */
-#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U /**< Counter Overflow */
-#define XTTCPS_IXR_ALL_MASK 0x0000001FU /**< All valid Interrupts */
-/* @} */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given Timer Counter register.
-*
-* @param BaseAddress is the base address of the timer counter device.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
- (Xil_In32((BaseAddress) + (u32)(RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Timer Counter register.
-*
-* @param BaseAddress is the base address of the timer counter device.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
-* u32 Data)
-*
-*****************************************************************************/
-#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
- (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
-
-/****************************************************************************/
-/**
-*
-* Calculate a match register offset using the Match Register index.
-*
-* @param MatchIndex is the 0-2 value of the match register
-*
-* @return MATCH_N_OFFSET.
-*
-* @note C-style signature:
-* u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
-*
-*****************************************************************************/
-#define XTtcPs_Match_N_Offset(MatchIndex) \
- ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/Makefile
deleted file mode 100644
index 68ad57aba..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=*.h
-LIBSOURCES=*.c
-OUTS = *.o
-
-libs:
- echo "Compiling pwm_recorder..."
- $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
- make clean
-
-include:
- ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
-
-clean:
- rm -rf ${OUTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.c
deleted file mode 100644
index bed446fbf..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.c
+++ /dev/null
@@ -1,6 +0,0 @@
-
-
-/***************************** Include Files *******************************/
-#include "pwm_recorder.h"
-
-/************************** Function Definitions ***************************/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.h
deleted file mode 100644
index cedcc1e50..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.h
+++ /dev/null
@@ -1,79 +0,0 @@
-
-#ifndef PWM_RECORDER_H
-#define PWM_RECORDER_H
-
-
-/****************** Include Files ********************/
-#include "xil_types.h"
-#include "xstatus.h"
-
-#define PWM_RECORDER_S_AXI_SLV_REG0_OFFSET 0
-#define PWM_RECORDER_S_AXI_SLV_REG1_OFFSET 4
-#define PWM_RECORDER_S_AXI_SLV_REG2_OFFSET 8
-#define PWM_RECORDER_S_AXI_SLV_REG3_OFFSET 12
-
-
-/**************************** Type Definitions *****************************/
-/**
- *
- * Write a value to a PWM_RECORDER register. A 32 bit write is performed.
- * If the component is implemented in a smaller width, only the least
- * significant data is written.
- *
- * @param BaseAddress is the base address of the PWM_RECORDERdevice.
- * @param RegOffset is the register offset from the base to write to.
- * @param Data is the data written to the register.
- *
- * @return None.
- *
- * @note
- * C-style signature:
- * void PWM_RECORDER_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
- *
- */
-#define PWM_RECORDER_mWriteReg(BaseAddress, RegOffset, Data) \
- Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/**
- *
- * Read a value from a PWM_RECORDER register. A 32 bit read is performed.
- * If the component is implemented in a smaller width, only the least
- * significant data is read from the register. The most significant data
- * will be read as 0.
- *
- * @param BaseAddress is the base address of the PWM_RECORDER device.
- * @param RegOffset is the register offset from the base to write to.
- *
- * @return Data is the data from the register.
- *
- * @note
- * C-style signature:
- * u32 PWM_RECORDER_mReadReg(u32 BaseAddress, unsigned RegOffset)
- *
- */
-#define PWM_RECORDER_mReadReg(BaseAddress, RegOffset) \
- Xil_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ****************************/
-/**
- *
- * Run a self-test on the driver/device. Note this may be a destructive test if
- * resets of the device are performed.
- *
- * If the hardware system is not built correctly, this function may never
- * return to the caller.
- *
- * @param baseaddr_p is the base address of the PWM_RECORDER instance to be worked on.
- *
- * @return
- *
- * - XST_SUCCESS if all self-test code passed
- * - XST_FAILURE if any self-test code failed
- *
- * @note Caching must be turned off for this function to work.
- * @note Self test may fail if data memory and device are not on the same bus.
- *
- */
-XStatus PWM_RECORDER_Reg_SelfTest(void * baseaddr_p);
-
-#endif // PWM_RECORDER_H
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder_selftest.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder_selftest.c
deleted file mode 100644
index 8f6d89fba..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder_selftest.c
+++ /dev/null
@@ -1,60 +0,0 @@
-
-/***************************** Include Files *******************************/
-#include "pwm_recorder.h"
-#include "xparameters.h"
-#include "stdio.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ***************************/
-#define READ_WRITE_MUL_FACTOR 0x10
-
-/************************** Function Definitions ***************************/
-/**
- *
- * Run a self-test on the driver/device. Note this may be a destructive test if
- * resets of the device are performed.
- *
- * If the hardware system is not built correctly, this function may never
- * return to the caller.
- *
- * @param baseaddr_p is the base address of the PWM_RECORDERinstance to be worked on.
- *
- * @return
- *
- * - XST_SUCCESS if all self-test code passed
- * - XST_FAILURE if any self-test code failed
- *
- * @note Caching must be turned off for this function to work.
- * @note Self test may fail if data memory and device are not on the same bus.
- *
- */
-XStatus PWM_RECORDER_Reg_SelfTest(void * baseaddr_p)
-{
- u32 baseaddr;
- int write_loop_index;
- int read_loop_index;
- int Index;
-
- baseaddr = (u32) baseaddr_p;
-
- xil_printf("******************************\n\r");
- xil_printf("* User Peripheral Self Test\n\r");
- xil_printf("******************************\n\n\r");
-
- /*
- * Write to user logic slave module register(s) and read back
- */
- xil_printf("User logic slave module test...\n\r");
-
- for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
- PWM_RECORDER_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
- for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
- if ( PWM_RECORDER_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
- xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
- return XST_FAILURE;
- }
-
- xil_printf(" - slave register write/read passed\n\n\r");
-
- return XST_SUCCESS;
-}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/Makefile
deleted file mode 100644
index 30682bc09..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=*.h
-LIBSOURCES=*.c
-OUTS = *.o
-
-libs:
- echo "Compiling pwm_signal_out..."
- $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
- make clean
-
-include:
- ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
-
-clean:
- rm -rf ${OUTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.c
deleted file mode 100644
index 5c5383eca..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.c
+++ /dev/null
@@ -1,6 +0,0 @@
-
-
-/***************************** Include Files *******************************/
-#include "pwm_signal_out.h"
-
-/************************** Function Definitions ***************************/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.h
deleted file mode 100644
index 4a80786f6..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.h
+++ /dev/null
@@ -1,79 +0,0 @@
-
-#ifndef PWM_SIGNAL_OUT_H
-#define PWM_SIGNAL_OUT_H
-
-
-/****************** Include Files ********************/
-#include "xil_types.h"
-#include "xstatus.h"
-
-#define PWM_SIGNAL_OUT_S_AXI_SLV_REG0_OFFSET 0
-#define PWM_SIGNAL_OUT_S_AXI_SLV_REG1_OFFSET 4
-#define PWM_SIGNAL_OUT_S_AXI_SLV_REG2_OFFSET 8
-#define PWM_SIGNAL_OUT_S_AXI_SLV_REG3_OFFSET 12
-
-
-/**************************** Type Definitions *****************************/
-/**
- *
- * Write a value to a PWM_SIGNAL_OUT register. A 32 bit write is performed.
- * If the component is implemented in a smaller width, only the least
- * significant data is written.
- *
- * @param BaseAddress is the base address of the PWM_SIGNAL_OUTdevice.
- * @param RegOffset is the register offset from the base to write to.
- * @param Data is the data written to the register.
- *
- * @return None.
- *
- * @note
- * C-style signature:
- * void PWM_SIGNAL_OUT_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
- *
- */
-#define PWM_SIGNAL_OUT_mWriteReg(BaseAddress, RegOffset, Data) \
- Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/**
- *
- * Read a value from a PWM_SIGNAL_OUT register. A 32 bit read is performed.
- * If the component is implemented in a smaller width, only the least
- * significant data is read from the register. The most significant data
- * will be read as 0.
- *
- * @param BaseAddress is the base address of the PWM_SIGNAL_OUT device.
- * @param RegOffset is the register offset from the base to write to.
- *
- * @return Data is the data from the register.
- *
- * @note
- * C-style signature:
- * u32 PWM_SIGNAL_OUT_mReadReg(u32 BaseAddress, unsigned RegOffset)
- *
- */
-#define PWM_SIGNAL_OUT_mReadReg(BaseAddress, RegOffset) \
- Xil_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ****************************/
-/**
- *
- * Run a self-test on the driver/device. Note this may be a destructive test if
- * resets of the device are performed.
- *
- * If the hardware system is not built correctly, this function may never
- * return to the caller.
- *
- * @param baseaddr_p is the base address of the PWM_SIGNAL_OUT instance to be worked on.
- *
- * @return
- *
- * - XST_SUCCESS if all self-test code passed
- * - XST_FAILURE if any self-test code failed
- *
- * @note Caching must be turned off for this function to work.
- * @note Self test may fail if data memory and device are not on the same bus.
- *
- */
-XStatus PWM_SIGNAL_OUT_Reg_SelfTest(void * baseaddr_p);
-
-#endif // PWM_SIGNAL_OUT_H
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out_selftest.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out_selftest.c
deleted file mode 100644
index f21e3dd81..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out_selftest.c
+++ /dev/null
@@ -1,60 +0,0 @@
-
-/***************************** Include Files *******************************/
-#include "pwm_signal_out.h"
-#include "xparameters.h"
-#include "stdio.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ***************************/
-#define READ_WRITE_MUL_FACTOR 0x10
-
-/************************** Function Definitions ***************************/
-/**
- *
- * Run a self-test on the driver/device. Note this may be a destructive test if
- * resets of the device are performed.
- *
- * If the hardware system is not built correctly, this function may never
- * return to the caller.
- *
- * @param baseaddr_p is the base address of the PWM_SIGNAL_OUTinstance to be worked on.
- *
- * @return
- *
- * - XST_SUCCESS if all self-test code passed
- * - XST_FAILURE if any self-test code failed
- *
- * @note Caching must be turned off for this function to work.
- * @note Self test may fail if data memory and device are not on the same bus.
- *
- */
-XStatus PWM_SIGNAL_OUT_Reg_SelfTest(void * baseaddr_p)
-{
- u32 baseaddr;
- int write_loop_index;
- int read_loop_index;
- int Index;
-
- baseaddr = (u32) baseaddr_p;
-
- xil_printf("******************************\n\r");
- xil_printf("* User Peripheral Self Test\n\r");
- xil_printf("******************************\n\n\r");
-
- /*
- * Write to user logic slave module register(s) and read back
- */
- xil_printf("User logic slave module test...\n\r");
-
- for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
- PWM_SIGNAL_OUT_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
- for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
- if ( PWM_SIGNAL_OUT_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
- xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
- return XST_FAILURE;
- }
-
- xil_printf(" - slave register write/read passed\n\n\r");
-
- return XST_SUCCESS;
-}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sleep.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sleep.h
deleted file mode 100644
index 27add6605..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sleep.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#ifndef SLEEP_H
-#define SLEEP_H
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-int usleep(unsigned long useconds);
-unsigned sleep(unsigned int seconds);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/Makefile
deleted file mode 100644
index 35c277dde..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES:=*.c
-INCLUDEFILES:=*.h
-
-OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
-
-libs: banner ttcps_libs clean
-
-%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
-
-banner:
- echo "Compiling ttcps"
-
-ttcps_libs: ${OBJECTS}
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
-
-.PHONY: include
-include: ttcps_includes
-
-ttcps_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps.c
deleted file mode 100644
index 394262868..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps.c
+++ /dev/null
@@ -1,443 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xttcps.c
-* @addtogroup ttcps_v3_0
-* @{
-*
-* This file contains the implementation of the XTtcPs driver. This driver
-* controls the operation of one timer counter in the Triple Timer Counter (TTC)
-* module in the Ps block. Refer to xttcps.h for more detailed description
-* of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -------------------------------------------------
-* 1.00a drg/jz 01/21/10 First release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.01 pkp 01/30/16 Modified XTtcPs_CfgInitialize to add XTtcps_Stop
-* to stop the timer before configuring
-* 3.2 mus 10/28/16 Modified XTtcPs_CalcIntervalFromFreq to calculate
-* 32 bit interval count for zynq ultrascale+mpsoc
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xttcps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Initializes a specific XTtcPs instance such that the driver is ready to use.
-* This function initializes a single timer counter in the triple timer counter
-* function block.
-*
-* The state of the device after initialization is:
-* - Overflow Mode
-* - Internal (pclk) selected
-* - Counter disabled
-* - All Interrupts disabled
-* - Output waveforms disabled
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-* @param ConfigPtr is a reference to a structure containing information
-* about a specific TTC device.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the address
-* mapping from EffectiveAddr to the device physical base address
-* unchanged once this function is invoked. Unexpected errors may
-* occur if the address mapping changes after this function is
-* called. If address translation is not used, then use
-* ConfigPtr->BaseAddress for this parameter, passing the physical
-* address instead.
-*
-* @return
-*
-* - XST_SUCCESS if the initialization is successful.
-* - XST_DEVICE_IS_STARTED if the device is started. It must be
-* stopped to re-initialize.
-*
-* @note Device has to be stopped first to call this function to
-* initialize it.
-*
-******************************************************************************/
-s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr,
- u32 EffectiveAddr)
-{
- s32 Status;
- u32 IsStartResult;
- /*
- * Assert to validate input arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
- /*
- * Set some default values
- */
- InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
- InstancePtr->Config.BaseAddress = EffectiveAddr;
- InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
-
- IsStartResult = XTtcPs_IsStarted(InstancePtr);
- /*
- * If the timer counter has already started, return an error
- * Device should be stopped first.
- */
- if(IsStartResult == (u32)TRUE) {
- Status = XST_DEVICE_IS_STARTED;
- } else {
-
- /*
- * stop the timer before configuring
- */
- XTtcPs_Stop(InstancePtr);
- /*
- * Reset the count control register to it's default value.
- */
- XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XTTCPS_CNT_CNTRL_OFFSET,
- XTTCPS_CNT_CNTRL_RESET_VALUE);
-
- /*
- * Reset the rest of the registers to the default values.
- */
- XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XTTCPS_CLK_CNTRL_OFFSET, 0x00U);
- XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XTTCPS_INTERVAL_VAL_OFFSET, 0x00U);
- XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XTTCPS_MATCH_1_OFFSET, 0x00U);
- XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XTTCPS_MATCH_2_OFFSET, 0x00U);
- XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XTTCPS_MATCH_2_OFFSET, 0x00U);
- XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XTTCPS_IER_OFFSET, 0x00U);
- XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XTTCPS_ISR_OFFSET, XTTCPS_IXR_ALL_MASK);
-
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- /*
- * Reset the counter value
- */
- XTtcPs_ResetCounterValue(InstancePtr);
- Status = XST_SUCCESS;
- }
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function is used to set the match registers. There are three match
-* registers.
-*
-* The match 0 register is special. If the waveform output mode is enabled, the
-* waveform will change polarity when the count matches the value in the match 0
-* register. The polarity of the waveform output can also be set using the
-* XTtcPs_SetOptions() function.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-* @param MatchIndex is the index to the match register to be set.
-* Valid values are 0, 1, or 2.
-* @param Value is the 16-bit value to be set in the match register.
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value)
-{
- /*
- * Assert to validate input arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(MatchIndex < (u8)XTTCPS_NUM_MATCH_REG);
-
- /*
- * Write the value to the correct match register with MatchIndex
- */
- XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XTtcPs_Match_N_Offset(MatchIndex), Value);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function is used to get the value of the match registers. There are
-* three match registers.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-* @param MatchIndex is the index to the match register to be set.
-* Valid values are 0, 1, or 2.
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex)
-{
- u32 MatchReg;
-
- /*
- * Assert to validate input arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(MatchIndex < XTTCPS_NUM_MATCH_REG);
-
- MatchReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XTtcPs_Match_N_Offset(MatchIndex));
-
- return (u16) MatchReg;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets the prescaler enable bit and if needed sets the prescaler
-* bits in the control register.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-* @param PrescalerValue is a number from 0-16 that sets the prescaler
-* to use.
-* If the parameter is 0 - 15, use a prescaler on the clock of
-* 2^(PrescalerValue+1), or 2-65536.
-* If the parameter is XTTCPS_CLK_CNTRL_PS_DISABLE, do not use a
-* prescaler.
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue)
-{
- u32 ClockReg;
-
- /*
- * Assert to validate input arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(PrescalerValue <= XTTCPS_CLK_CNTRL_PS_DISABLE);
-
- /*
- * Read the clock control register
- */
- ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XTTCPS_CLK_CNTRL_OFFSET);
-
- /*
- * Clear all of the prescaler control bits in the register
- */
- ClockReg &=
- ~(XTTCPS_CLK_CNTRL_PS_VAL_MASK | XTTCPS_CLK_CNTRL_PS_EN_MASK);
-
- if (PrescalerValue < XTTCPS_CLK_CNTRL_PS_DISABLE) {
- /*
- * Set the prescaler value and enable prescaler
- */
- ClockReg |= (u32)(((u32)PrescalerValue << (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT) &
- (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK);
- ClockReg |= (u32)XTTCPS_CLK_CNTRL_PS_EN_MASK;
- }
-
- /*
- * Write the register with the new values.
- */
- XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the input clock prescaler
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-*
-* <pre>
-* @return The value(n) from which the prescalar value is calculated
-* as 2^(n+1). Some example values are given below :
-*
-* Value Prescaler
-* 0 2
-* 1 4
-* N 2^(n+1)
-* 15 65536
-* 16 1
-* </pre>
-*
-* @note None.
-*
-****************************************************************************/
-u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr)
-{
- u8 Status;
- u32 ClockReg;
-
- /*
- * Assert to validate input arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the clock control register
- */
- ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XTTCPS_CLK_CNTRL_OFFSET);
-
- if (0 == (ClockReg & XTTCPS_CLK_CNTRL_PS_EN_MASK)) {
- /*
- * Prescaler is disabled. Return the correct flag value
- */
- Status = (u8)XTTCPS_CLK_CNTRL_PS_DISABLE;
- }
- else {
-
- Status = (u8)((ClockReg & (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK) >>
- (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT);
- }
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function calculates the interval value as well as the prescaler value
-* for a given frequency.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-* @param Freq is the requested output frequency for the device.
-* @param Interval is the interval value for the given frequency,
-* it is the output value for this function.
-* @param Prescaler is the prescaler value for the given frequency,
-* it is the output value for this function.
-*
-* @return None.
-*
-* @note
-* Upon successful calculation for the given frequency, Interval and Prescaler
-* carry the settings for the timer counter; Upon unsuccessful calculation,
-* Interval and Prescaler are set to 0xFF(FF) for their maximum values to
-* signal the caller of failure. Therefore, caller needs to check the return
-* interval or prescaler values for whether the function has succeeded.
-*
-****************************************************************************/
-void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
- XInterval *Interval, u8 *Prescaler)
-{
- u8 TmpPrescaler;
- u32 TempValue;
- u32 InputClock;
-
- InputClock = InstancePtr->Config.InputClockHz;
- /*
- * Find the smallest prescaler that will work for a given frequency. The
- * smaller the prescaler, the larger the count and the more accurate the
- * PWM setting.
- */
- TempValue = InputClock/ Freq;
-
- if (TempValue < 4U) {
- /*
- * The frequency is too high, it is too close to the input
- * clock value. Use maximum values to signal caller.
- */
- *Interval = XTTCPS_MAX_INTERVAL_COUNT;
- *Prescaler = 0xFFU;
- return;
- }
-
- /*
- * First, do we need a prescaler or not?
- */
- if (((u32)65536U) > TempValue) {
- /*
- * We do not need a prescaler, so set the values appropriately
- */
- *Interval = (XInterval)TempValue;
- *Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE;
- return;
- }
-
-
- for (TmpPrescaler = 0U; TmpPrescaler < XTTCPS_CLK_CNTRL_PS_DISABLE;
- TmpPrescaler++) {
- TempValue = InputClock/ (Freq * (1U << (TmpPrescaler + 1U)));
-
- /*
- * The first value less than 2^16 is the best bet
- */
- if (((u32)65536U) > TempValue) {
- /*
- * Set the values appropriately
- */
- *Interval = (XInterval)TempValue;
- *Prescaler = TmpPrescaler;
- return;
- }
- }
-
- /* Can not find interval values that work for the given frequency.
- * Return maximum values to signal caller.
- */
- *Interval = XTTCPS_MAX_INTERVAL_COUNT;
- *Prescaler = 0XFFU;
- return;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps.h
deleted file mode 100644
index bae9d28fe..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps.h
+++ /dev/null
@@ -1,466 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xttcps.h
-* @addtogroup ttcps_v3_0
-* @{
-* @details
-*
-* This is the driver for one 16-bit timer counter in the Triple Timer Counter
-* (TTC) module in the Ps block.
-*
-* The TTC module provides three independent timer/counter modules that can each
-* be clocked using either the system clock (pclk) or an externally driven
-* clock (ext_clk). In addition, each counter can independently prescale its
-* selected clock input (divided by 2 to 65536). Counters can be set to
-* decrement or increment.
-*
-* Each of the counters can be programmed to generate interrupt pulses:
-* . At a regular, predefined period, that is on a timed interval
-* . When the counter registers overflow
-* . When the count matches any one of the three 'match' registers
-*
-* Therefore, up to six different events can trigger a timer interrupt: three
-* match interrupts, an overflow interrupt, an interval interrupt and an event
-* timer interrupt. Note that the overflow interrupt and the interval interrupt
-* are mutually exclusive.
-*
-* <b>Initialization & Configuration</b>
-*
-* An XTtcPs_Config structure is used to configure a driver instance.
-* Information in the XTtcPs_Config structure is the hardware properties
-* about the device.
-*
-* A driver instance is initialized through
-* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
-* is a pointer to the XTtcPs_Config structure, it can be looked up statically
-* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
-* EffectiveAddr can be the static base address of the device or virtual
-* mapped address if address translation is supported.
-*
-* <b>Interrupts</b>
-*
-* Interrupt handler is not provided by the driver, as handling of interrupt
-* is application specific.
-*
-* @note
-* The default setting for a timer/counter is:
-* - Overflow Mode
-* - Internal clock (pclk) selected
-* - Counter disabled
-* - All Interrupts disabled
-* - Output waveforms disabled
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------------
-* 1.00a drg/jz 01/20/10 First release..
-* 2.0 adk 12/10/13 Updated as per the New Tcl API's
-* 3.0 pkp 12/09/14 Added support for Zynq Ultrascale Mp.Also code
-* modified for MISRA-C:2012 compliance.
-* 3.2 mus 10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
-* macros to return 32 bit values for zynq ultrascale+mpsoc
-* ms 01/23/17 Modified xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTTCPS_H /* prevent circular inclusions */
-#define XTTCPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xttcps_hw.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-/*
- * Flag for a9 processor
- */
- #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
- #define ARMA9
- #endif
-
-/*
- * Maximum Value for interval counter
- */
- #if defined(ARMA9)
- #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU
- #else
- #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU
- #endif
-
-/** @name Configuration options
- *
- * Options for the device. Each of the options is bit field, so more than one
- * options can be specified.
- *
- * @{
- */
-#define XTTCPS_OPTION_EXTERNAL_CLK 0x00000001U /**< External clock source */
-#define XTTCPS_OPTION_CLK_EDGE_NEG 0x00000002U /**< Clock on trailing edge for
- external clock*/
-#define XTTCPS_OPTION_INTERVAL_MODE 0x00000004U /**< Interval mode */
-#define XTTCPS_OPTION_DECREMENT 0x00000008U /**< Decrement the counter */
-#define XTTCPS_OPTION_MATCH_MODE 0x00000010U /**< Match mode */
-#define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U /**< No waveform output */
-#define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U /**< Waveform polarity */
-/*@}*/
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID for device */
- u32 BaseAddress; /**< Base address for device */
- u32 InputClockHz; /**< Input clock frequency */
-} XTtcPs_Config;
-
-/**
- * The XTtcPs driver instance data. The user is required to allocate a
- * variable of this type for each PS timer/counter device in the system. A
- * pointer to a variable of this type is then passed to various driver API
- * functions.
- */
-typedef struct {
- XTtcPs_Config Config; /**< Configuration structure */
- u32 IsReady; /**< Device is initialized and ready */
-} XTtcPs;
-
-/**
- * This typedef contains interval count
- */
-#if defined(ARMA9)
-typedef u16 XInterval;
-#else
-typedef u32 XInterval;
-#endif
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*
- * Internal helper macros
- */
-#define InstReadReg(InstancePtr, RegOffset) \
- (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
-
-#define InstWriteReg(InstancePtr, RegOffset, Data) \
- (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
-
-/*****************************************************************************/
-/**
-*
-* This function starts the counter/timer without resetting the counter value.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return None
-*
-* @note C-style signature:
-* void XTtcPs_Start(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#define XTtcPs_Start(InstancePtr) \
- InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
- (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
- ~XTTCPS_CNT_CNTRL_DIS_MASK))
-
-/*****************************************************************************/
-/**
-*
-* This function stops the counter/timer. This macro may be called at any time
-* to stop the counter. The counter holds the last value until it is reset,
-* restarted or enabled.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return None
-*
-* @note C-style signature:
-* void XTtcPs_Stop(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#define XTtcPs_Stop(InstancePtr) \
- InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
- (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
- XTTCPS_CNT_CNTRL_DIS_MASK))
-
-/*****************************************************************************/
-/**
-*
-* This function checks whether the timer counter has already started.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance
-*
-* @return Non-zero if the device has started, '0' otherwise.
-*
-* @note C-style signature:
-* int XTtcPs_IsStarted(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#define XTtcPs_IsStarted(InstancePtr) \
- ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
- XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
-
-/*****************************************************************************/
-/**
-*
-* This function returns the current 16-bit counter value. It may be called at
-* any time.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return zynq:16 bit counter value.
-* zynq ultrascale+mpsoc:32 bit counter value.
-*
-* @note C-style signature:
-* zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
-* zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#if defined(ARMA9)
-/*
- * ttc supports 16 bit counter for zynq
- */
-#define XTtcPs_GetCounterValue(InstancePtr) \
- (u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
-#else
-/*
- * ttc supports 32 bit counter for zynq ultrascale+mpsoc
- */
-#define XTtcPs_GetCounterValue(InstancePtr) \
- InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This function sets the interval value to be used in interval mode.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-* @param Value is the 16-bit value to be set in the interval register.
-*
-* @return None
-*
-* @note C-style signature:
-* void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value)
-*
-****************************************************************************/
-#define XTtcPs_SetInterval(InstancePtr, Value) \
- InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
-
-/*****************************************************************************/
-/**
-*
-* This function gets the interval value from the interval register.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return zynq:16 bit interval value.
-* zynq ultrascale+mpsoc:32 bit interval value.
-*
-* @note C-style signature:
-* zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
-* zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#if defined(ARMA9)
-/*
- * ttc supports 16 bit interval counter for zynq
- */
-#define XTtcPs_GetInterval(InstancePtr) \
- (u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
-#else
-/*
- * ttc supports 32 bit interval counter for zynq ultrascale+mpsoc
- */
-#define XTtcPs_GetInterval(InstancePtr) \
- InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
-#endif
-/*****************************************************************************/
-/**
-*
-* This macro resets the count register. It may be called at any time. The
-* counter is reset to either 0 or 0xFFFF, or the interval value, depending on
-* the increment/decrement mode. The state of the counter, as started or
-* stopped, is not affected by calling reset.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return None
-*
-* @note C-style signature:
-* void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
-*
-****************************************************************************/
-#define XTtcPs_ResetCounterValue(InstancePtr) \
- InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
- (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
- (u32)XTTCPS_CNT_CNTRL_RST_MASK))
-
-/*****************************************************************************/
-/**
-*
-* This function enables the interrupts.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-* @param InterruptMask defines which interrupt should be enabled.
-* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
-* This is a bit mask, all set bits will be enabled, cleared bits
-* will not be disabled.
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
-*
-******************************************************************************/
-#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask) \
- InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
- (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) | \
- (InterruptMask)))
-
-/*****************************************************************************/
-/**
-*
-* This function disables the interrupts.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-* @param InterruptMask defines which interrupt should be disabled.
-* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
-* This is a bit mask, all set bits will be disabled, cleared bits
-* will not be disabled.
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
-*
-******************************************************************************/
-#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
- InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
- (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) & \
- ~(InterruptMask)))
-
-/*****************************************************************************/
-/**
-*
-* This function reads the interrupt status.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
-*
-******************************************************************************/
-#define XTtcPs_GetInterruptStatus(InstancePtr) \
- InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
-
-/*****************************************************************************/
-/**
-*
-* This function clears the interrupt status.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-* @param InterruptMask defines which interrupt should be cleared.
-* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
-* This is a bit mask, all set bits will be cleared, cleared bits
-* will not be cleared.
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
-*
-******************************************************************************/
-#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
- InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \
- (InterruptMask))
-
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Initialization functions in xttcps_sinit.c
- */
-XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
-
-/*
- * Required functions, in xttcps.c
- */
-s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
- XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
-
-void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value);
-u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
-
-void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
-u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
-
-void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
- XInterval *Interval, u8 *Prescaler);
-
-/*
- * Functions for options, in file xttcps_options.c
- */
-s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
-u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
-
-/*
- * Function for self-test, in file xttcps_selftest.c
- */
-s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_g.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_g.c
deleted file mode 100644
index 682ac8178..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_g.c
+++ /dev/null
@@ -1,66 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version:
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
-*Permission is hereby granted, free of charge, to any person obtaining a copy
-*of this software and associated documentation files (the Software), to deal
-*in the Software without restriction, including without limitation the rights
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-*copies of the Software, and to permit persons to whom the Software is
-*furnished to do so, subject to the following conditions:
-*
-*The above copyright notice and this permission notice shall be included in
-*all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-*(a) running on a Xilinx device, or
-*(b) that interact with a Xilinx device through a bus or interconnect.
-*
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-*Except as contained in this notice, the name of the Xilinx shall not be used
-*in advertising or otherwise to promote the sale, use or other dealings in
-*this Software without prior written authorization from Xilinx.
-*
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xttcps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XTtcPs_Config XTtcPs_ConfigTable[] =
-{
- {
- XPAR_PS7_TTC_0_DEVICE_ID,
- XPAR_PS7_TTC_0_BASEADDR,
- XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ
- },
- {
- XPAR_PS7_TTC_1_DEVICE_ID,
- XPAR_PS7_TTC_1_BASEADDR,
- XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ
- },
- {
- XPAR_PS7_TTC_2_DEVICE_ID,
- XPAR_PS7_TTC_2_BASEADDR,
- XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ
- }
-};
-
-
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_hw.h
deleted file mode 100644
index af78bcd67..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_hw.h
+++ /dev/null
@@ -1,212 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xttcps_hw.h
-* @addtogroup ttcps_v3_0
-* @{
-*
-* This file defines the hardware interface to one of the three timer counters
-* in the Ps block.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -------------------------------------------------
-* 1.00a drg/jz 01/21/10 First release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTTCPS_HW_H /* prevent circular inclusions */
-#define XTTCPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of the device.
- *
- * @{
- */
-#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U /**< Clock Control Register */
-#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU /**< Counter Control Register*/
-#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U /**< Current Counter Value */
-#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U /**< Interval Count Value */
-#define XTTCPS_MATCH_0_OFFSET 0x00000030U /**< Match 1 value */
-#define XTTCPS_MATCH_1_OFFSET 0x0000003CU /**< Match 2 value */
-#define XTTCPS_MATCH_2_OFFSET 0x00000048U /**< Match 3 value */
-#define XTTCPS_ISR_OFFSET 0x00000054U /**< Interrupt Status Register */
-#define XTTCPS_IER_OFFSET 0x00000060U /**< Interrupt Enable Register */
-/* @} */
-
-/** @name Clock Control Register
- * Clock Control Register definitions
- * @{
- */
-#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U /**< Prescale enable */
-#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU /**< Prescale value */
-#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U /**< Prescale shift */
-#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U /**< Prescale disable */
-#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U /**< Clock source */
-#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U /**< External Clock edge */
-/* @} */
-
-/** @name Counter Control Register
- * Counter Control Register definitions
- * @{
- */
-#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U /**< Disable the counter */
-#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U /**< Interval mode */
-#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U /**< Decrement mode */
-#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U /**< Match mode */
-#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U /**< Reset counter */
-#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U /**< Enable waveform */
-#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U /**< Waveform polarity */
-#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U /**< Reset value */
-/* @} */
-
-/** @name Current Counter Value Register
- * Current Counter Value Register definitions
- * @{
- */
-#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU /**< 16-bit counter value */
-/* @} */
-
-/** @name Interval Value Register
- * Interval Value Register is the maximum value the counter will count up or
- * down to.
- * @{
- */
-#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU /**< 16-bit Interval value*/
-/* @} */
-
-/** @name Match Registers
- * Definitions for Match registers, each timer counter has three match
- * registers.
- * @{
- */
-#define XTTCPS_MATCH_MASK 0x0000FFFFU /**< 16-bit Match value */
-#define XTTCPS_NUM_MATCH_REG 3U /**< Num of Match reg */
-/* @} */
-
-/** @name Interrupt Registers
- * Following register bit mask is for all interrupt registers.
- *
- * @{
- */
-#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U /**< Interval Interrupt */
-#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U /**< Match 1 Interrupt */
-#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U /**< Match 2 Interrupt */
-#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U /**< Match 3 Interrupt */
-#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U /**< Counter Overflow */
-#define XTTCPS_IXR_ALL_MASK 0x0000001FU /**< All valid Interrupts */
-/* @} */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given Timer Counter register.
-*
-* @param BaseAddress is the base address of the timer counter device.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
- (Xil_In32((BaseAddress) + (u32)(RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Timer Counter register.
-*
-* @param BaseAddress is the base address of the timer counter device.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
-* u32 Data)
-*
-*****************************************************************************/
-#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
- (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
-
-/****************************************************************************/
-/**
-*
-* Calculate a match register offset using the Match Register index.
-*
-* @param MatchIndex is the 0-2 value of the match register
-*
-* @return MATCH_N_OFFSET.
-*
-* @note C-style signature:
-* u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
-*
-*****************************************************************************/
-#define XTtcPs_Match_N_Offset(MatchIndex) \
- ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-#endif /* end of protection macro */
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_options.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_options.c
deleted file mode 100644
index 532b235c5..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_options.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xttcps_options.c
-* @addtogroup ttcps_v3_0
-* @{
-*
-* This file contains functions to get or set option features for the device.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------
-* 1.00a drg/jz 01/21/10 First release
-* 1.01a nm 03/05/2012 Removed break statement after return to remove
-* compilation warnings.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xttcps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-/*
- * Create the table of options which are processed to get/set the device
- * options. These options are table driven to allow easy maintenance and
- * expansion of the options.
- */
-typedef struct {
- u32 Option;
- u32 Mask;
- u32 Register;
-} OptionsMap;
-
-static OptionsMap TmrCtrOptionsTable[] = {
- {XTTCPS_OPTION_EXTERNAL_CLK, XTTCPS_CLK_CNTRL_SRC_MASK,
- XTTCPS_CLK_CNTRL_OFFSET},
- {XTTCPS_OPTION_CLK_EDGE_NEG, XTTCPS_CLK_CNTRL_EXT_EDGE_MASK,
- XTTCPS_CLK_CNTRL_OFFSET},
- {XTTCPS_OPTION_INTERVAL_MODE, XTTCPS_CNT_CNTRL_INT_MASK,
- XTTCPS_CNT_CNTRL_OFFSET},
- {XTTCPS_OPTION_DECREMENT, XTTCPS_CNT_CNTRL_DECR_MASK,
- XTTCPS_CNT_CNTRL_OFFSET},
- {XTTCPS_OPTION_MATCH_MODE, XTTCPS_CNT_CNTRL_MATCH_MASK,
- XTTCPS_CNT_CNTRL_OFFSET},
- {XTTCPS_OPTION_WAVE_DISABLE, XTTCPS_CNT_CNTRL_EN_WAVE_MASK,
- XTTCPS_CNT_CNTRL_OFFSET},
- {XTTCPS_OPTION_WAVE_POLARITY, XTTCPS_CNT_CNTRL_POL_WAVE_MASK,
- XTTCPS_CNT_CNTRL_OFFSET},
-};
-
-#define XTTCPS_NUM_TMRCTR_OPTIONS (sizeof(TmrCtrOptionsTable) / \
- sizeof(OptionsMap))
-
-/*****************************************************************************/
-/**
-*
-* This function sets the options for the TTC device.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-* @param Options contains the specified options to be set. This is a bit
-* mask where a 1 means to turn the option on, and a 0 means to
-* turn the option off. One or more bit values may be contained
-* in the mask. See the bit definitions named XTTCPS_*_OPTION in
-* the file xttcps.h.
-*
-* @return
-* - XST_SUCCESS if options are successfully set.
-* - XST_FAILURE if any of the options are unknown.
-*
-* @note None
-*
-******************************************************************************/
-s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
-{
- u32 CountReg;
- u32 ClockReg;
- u32 Index;
- s32 Status = XST_SUCCESS;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XTTCPS_CLK_CNTRL_OFFSET);
- CountReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XTTCPS_CNT_CNTRL_OFFSET);
-
- /*
- * Loop through the options table, turning the option on or off
- * depending on whether the bit is set in the incoming options flag.
- */
- for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
- if(Status != (s32)XST_FAILURE) {
- if ((Options & TmrCtrOptionsTable[Index].Option) != (u32)0) {
-
- switch (TmrCtrOptionsTable[Index].Register) {
-
- case XTTCPS_CLK_CNTRL_OFFSET:
- /* Add option */
- ClockReg |= TmrCtrOptionsTable[Index].Mask;
- break;
-
- case XTTCPS_CNT_CNTRL_OFFSET:
- /* Add option */
- CountReg |= TmrCtrOptionsTable[Index].Mask;
- break;
-
- default:
- Status = XST_FAILURE;
- break;
- }
- }
- else {
- switch (TmrCtrOptionsTable[Index].Register) {
-
- case XTTCPS_CLK_CNTRL_OFFSET:
- /* Remove option*/
- ClockReg &= ~TmrCtrOptionsTable[Index].Mask;
- break;
-
- case XTTCPS_CNT_CNTRL_OFFSET:
- /* Remove option*/
- CountReg &= ~TmrCtrOptionsTable[Index].Mask;
- break;
-
- default:
- Status = XST_FAILURE;
- break;
- }
- }
- }
- }
-
- /*
- * Now write the registers. Leave it to the upper layers to restart the
- * device.
- */
- if (Status != (s32)XST_FAILURE ) {
- XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
- XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XTTCPS_CNT_CNTRL_OFFSET, CountReg);
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the settings for the options for the TTC device.
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return
-*
-* The return u32 contains the specified options that are set. This is a bit
-* mask where a '1' means the option is on, and a'0' means the option is off.
-* One or more bit values may be contained in the mask. See the bit definitions
-* named XTTCPS_*_OPTION in the file xttcps.h.
-*
-* @note None.
-*
-******************************************************************************/
-u32 XTtcPs_GetOptions(XTtcPs *InstancePtr)
-{
- u32 OptionsFlag = 0U;
- u32 Register;
- u32 Index;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- /*
- * Loop through the options table to determine which options are set
- */
- for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
- /*
- * Get the control register to determine which options are
- * currently set.
- */
- Register = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
- TmrCtrOptionsTable[Index].
- Register);
-
- if ((Register & TmrCtrOptionsTable[Index].Mask) != (u32)0) {
- OptionsFlag |= TmrCtrOptionsTable[Index].Option;
- }
- }
-
- return OptionsFlag;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_selftest.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_selftest.c
deleted file mode 100644
index 4923df667..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_selftest.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xttcps_selftest.c
-* @addtogroup ttcps_v3_0
-* @{
-*
-* This file contains the implementation of self test function for the
-* XTtcPs driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------
-* 1.00a drg/jz 01/21/10 First release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xttcps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Runs a self-test on the driver/device.
-*
-*
-* @param InstancePtr is a pointer to the XTtcPs instance.
-*
-* @return
-*
-* - XST_SUCCESS if successful
-* - XST_FAILURE indicates a register did not read or write correctly
-*
-* @note This test fails if it is not called right after initialization.
-*
-******************************************************************************/
-s32 XTtcPs_SelfTest(XTtcPs *InstancePtr)
-{
- s32 Status;
- u32 TempReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * All the TTC registers should be in their default state right now.
- */
- TempReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XTTCPS_CNT_CNTRL_OFFSET);
- if (XTTCPS_CNT_CNTRL_RESET_VALUE != (u32)TempReg) {
- Status = XST_FAILURE;
- }
- else {
- Status = XST_SUCCESS;
- }
- return Status;
-}
-/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/system.mss b/quad/xsdk_workspace_vivado/standalone_bsp_0/system.mss
deleted file mode 100644
index 5f6ae5d99..000000000
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/system.mss
+++ /dev/null
@@ -1,315 +0,0 @@
-
- PARAMETER VERSION = 2.2.0
-
-
-BEGIN OS
- PARAMETER OS_NAME = standalone
- PARAMETER OS_VER = 6.2
- PARAMETER PROC_INSTANCE = ps7_cortexa9_0
- PARAMETER stdin = ps7_uart_0
- PARAMETER stdout = ps7_uart_0
-END
-
-
-BEGIN PROCESSOR
- PARAMETER DRIVER_NAME = cpu_cortexa9
- PARAMETER DRIVER_VER = 2.4
- PARAMETER HW_INSTANCE = ps7_cortexa9_0
-END
-
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = gpio
- PARAMETER DRIVER_VER = 4.3
- PARAMETER HW_INSTANCE = axi_gpio_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = gpio
- PARAMETER DRIVER_VER = 4.3
- PARAMETER HW_INSTANCE = axi_gpio_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_afi_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_afi_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_afi_2
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_afi_3
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = coresightps_dcc
- PARAMETER DRIVER_VER = 1.4
- PARAMETER HW_INSTANCE = ps7_coresight_comp_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = ddrps
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = ps7_ddr_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_ddrc_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = devcfg
- PARAMETER DRIVER_VER = 3.4
- PARAMETER HW_INSTANCE = ps7_dev_cfg_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = dmaps
- PARAMETER DRIVER_VER = 2.3
- PARAMETER HW_INSTANCE = ps7_dma_ns
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = dmaps
- PARAMETER DRIVER_VER = 2.3
- PARAMETER HW_INSTANCE = ps7_dma_s
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = emacps
- PARAMETER DRIVER_VER = 3.4
- PARAMETER HW_INSTANCE = ps7_ethernet_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_globaltimer_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = gpiops
- PARAMETER DRIVER_VER = 3.2
- PARAMETER HW_INSTANCE = ps7_gpio_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_gpv_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 3.5
- PARAMETER HW_INSTANCE = ps7_i2c_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 3.5
- PARAMETER HW_INSTANCE = ps7_i2c_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_intc_dist_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_iop_bus_config_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_l2cachec_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_ocmc_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_pl310_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_pmu_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = qspips
- PARAMETER DRIVER_VER = 3.3
- PARAMETER HW_INSTANCE = ps7_qspi_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_qspi_linear_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_ram_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_ram_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_scuc_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = scugic
- PARAMETER DRIVER_VER = 3.6
- PARAMETER HW_INSTANCE = ps7_scugic_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = scutimer
- PARAMETER DRIVER_VER = 2.1
- PARAMETER HW_INSTANCE = ps7_scutimer_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = scuwdt
- PARAMETER DRIVER_VER = 2.1
- PARAMETER HW_INSTANCE = ps7_scuwdt_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = sdps
- PARAMETER DRIVER_VER = 3.2
- PARAMETER HW_INSTANCE = ps7_sd_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = ps7_slcr_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.3
- PARAMETER HW_INSTANCE = ps7_ttc_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 3.4
- PARAMETER HW_INSTANCE = ps7_uart_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 3.4
- PARAMETER HW_INSTANCE = ps7_uart_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = usbps
- PARAMETER DRIVER_VER = 2.4
- PARAMETER HW_INSTANCE = ps7_usb_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = xadcps
- PARAMETER DRIVER_VER = 2.2
- PARAMETER HW_INSTANCE = ps7_xadc_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_recorder
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_recorder_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_recorder
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_recorder_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_recorder
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_recorder_2
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_recorder
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_recorder_3
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_recorder
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_recorder_4
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_recorder
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_recorder_5
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_signal_out
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_signal_out_0
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_signal_out
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_signal_out_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_signal_out
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_signal_out_2
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = pwm_signal_out
- PARAMETER DRIVER_VER = 1.0
- PARAMETER HW_INSTANCE = pwm_signal_out_3
-END
-
-
diff --git a/quad/xsdk_workspace_vivado/system_bsp/.cproject b/quad/xsdk_workspace_vivado/system_bsp/.cproject
index 040b9d963..42bf4a9ac 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/.cproject
+++ b/quad/xsdk_workspace_vivado/system_bsp/.cproject
@@ -1,8 +1,8 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="org.eclipse.cdt.core.default.config.208777439">
- <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.208777439" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
+ <cconfiguration id="org.eclipse.cdt.core.default.config.2090257826">
+ <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.2090257826" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/>
<extensions/>
</storageModule>
@@ -10,6 +10,4 @@
</cconfiguration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
- <storageModule moduleId="refreshScope"/>
- <storageModule moduleId="org.eclipse.cdt.core.pathentry"/>
</cproject>
diff --git a/quad/xsdk_workspace_vivado/system_bsp/.project b/quad/xsdk_workspace_vivado/system_bsp/.project
index 0c80fba07..1773c9f5f 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/.project
+++ b/quad/xsdk_workspace_vivado/system_bsp/.project
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>system_bsp</name>
- <comment>Created by SDK v2017.1</comment>
+ <comment>Created by SDK v2018.2</comment>
<projects>
</projects>
<buildSpec>
diff --git a/quad/xsdk_workspace_vivado/system_bsp/.sdkproject b/quad/xsdk_workspace_vivado/system_bsp/.sdkproject
index 6e301ca60..dd82e57dd 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/.sdkproject
+++ b/quad/xsdk_workspace_vivado/system_bsp/.sdkproject
@@ -1,4 +1,4 @@
THIRPARTY=false
-HW_PROJECT_REFERENCE=quad_wrapper_hw_platform_0
+HW_PROJECT_REFERENCE=design_1_wrapper_hw_platform_0
PROCESSOR=ps7_cortexa9_0
MSS_FILE=system.mss
diff --git a/quad/xsdk_workspace_vivado/system_bsp/Makefile b/quad/xsdk_workspace_vivado/system_bsp/Makefile
index 1ace345f6..1e68922ca 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/Makefile
+++ b/quad/xsdk_workspace_vivado/system_bsp/Makefile
@@ -23,11 +23,11 @@ $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
@echo "Running Make include in $(subst /make.include,,$@)"
- $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -Wall -Wextra"
+ $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
%/make.libs: include
@echo "Running Make libs in $(subst /make.libs,,$@)"
- $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -Wall -Wextra"
+ $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
%/make.clean:
$(MAKE) -C $(subst /make.clean,,$@) -s clean
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/_profile_timer_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/_profile_timer_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/bspconfig.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/bspconfig.h
similarity index 89%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/bspconfig.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/bspconfig.h
index 87363749e..b977241ce 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/bspconfig.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/bspconfig.h
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@@ -37,4 +37,9 @@
*
*******************************************************************/
+#ifndef BSPCONFIG_H /* prevent circular inclusions */
+#define BSPCONFIG_H /* by using protection macros */
+
#define MICROBLAZE_PVR_NONE
+
+#endif /*end of __BSPCONFIG_H_*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/mblaze_nt_types.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/mblaze_nt_types.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/profile.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/profile.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/profile.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/profile.h
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/src/pwm_recorder.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/pwm_recorder.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/src/pwm_recorder.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/pwm_recorder.h
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/src/pwm_signal_out.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/pwm_signal_out.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/src/pwm_signal_out.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/pwm_signal_out.h
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/sleep.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/sleep.h
new file mode 100644
index 000000000..f53b2d8c8
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/sleep.h
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file sleep.h
+*
+* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
+* related APIs.
+*
+* <pre>
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 11/02/17 Added processor specific sleep rountines
+* function prototypes.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This macro polls an address periodically until a condition is met or till the
+* timeout occurs.
+* The minimum timeout for calling this macro is 100us. If the timeout is less
+* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
+* If the timeout is not a multiple of 100us, it waits for a timeout of
+* the next usec value which is a multiple of 100us.
+*
+* @param IO_func - accessor function to read the register contents.
+* Depends on the register width.
+* @param ADDR - Address to be polled
+* @param VALUE - variable to read the value
+* @param COND - Condition to checked (usually involves VALUE)
+* @param TIMEOUT_US - timeout in micro seconds
+*
+* @return 0 - when the condition is met
+* -1 - when the condition is not met till the timeout period
+*
+* @note none
+*
+*****************************************************************************/
+#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
+ ( { \
+ u64 timeout = TIMEOUT_US/100; \
+ if(TIMEOUT_US%100!=0) \
+ timeout++; \
+ for(;;) { \
+ VALUE = IO_func(ADDR); \
+ if(COND) \
+ break; \
+ else { \
+ usleep(100); \
+ timeout--; \
+ if(timeout==0) \
+ break; \
+ } \
+ } \
+ (timeout>0) ? 0 : -1; \
+ } )
+
+void usleep(unsigned long useconds);
+void sleep(unsigned int seconds);
+int usleep_R5(unsigned long useconds);
+unsigned sleep_R5(unsigned int seconds);
+int usleep_MB(unsigned long useconds);
+unsigned sleep_MB(unsigned int seconds);
+int usleep_A53(unsigned long useconds);
+unsigned sleep_A53(unsigned int seconds);
+int usleep_A9(unsigned long useconds);
+unsigned sleep_A9(unsigned int seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/smc.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/smc.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/smc.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/smc.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/vectors.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/vectors.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/vectors.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/vectors.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xadcps.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xadcps.h
index 9b6737d37..549bfff29 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xadcps.h
@@ -176,7 +176,9 @@
* for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
-*
+* ms 04/05/17 Modified Comment lines in functions of xadcps
+* examples to recognize it as documentation block
+* for doxygen generation.
*
* </pre>
*
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xadcps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xadcps_hw.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xadcps_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xadcps_hw.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xbasic_types.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xbasic_types.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xbasic_types.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xbasic_types.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h
index a732b235d..67959e327 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h
@@ -33,7 +33,7 @@
/**
*
* @file xcoresightpsdcc.h
-* @addtogroup coresightps_dcc_v1_1
+* @addtogroup coresightps_dcc_v1_4
* @{
* @details
*
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_4/src/xcpu_cortexa9.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h
similarity index 86%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_4/src/xcpu_cortexa9.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h
index 4d441e53e..95c8ba536 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_4/src/xcpu_cortexa9.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h
@@ -33,11 +33,16 @@
/**
*
* @file xcpu_cortexa9.h
-* @addtogroup cpu_cortexa9_v2_1
+* @addtogroup cpu_cortexa9_v2_5
* @{
* @details
*
* dummy file
+* MODIFICATION HISTORY:
*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
+* parameter of cpu_cortexa9 in xparameters.h
******************************************************************************/
/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xddrps.h
similarity index 96%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xddrps.h
index fe7adb066..c8804d2ed 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xddrps.h
@@ -18,8 +18,8 @@
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdebug.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdebug.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdebug.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdebug.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdevcfg.h
similarity index 97%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdevcfg.h
index 7fc1332a5..b9a0111d6 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdevcfg.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xdevcfg.h
-* @addtogroup devcfg_v3_3
+* @addtogroup devcfg_v3_5
* @{
* @details
*
@@ -154,7 +154,11 @@
* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
-*
+* ms 04/10/17 Modified filename tag in interrupt and polled examples
+* to include them in doxygen examples.
+* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
+* definitions of devcfg in xparameters.h
+* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
* </pre>
*
******************************************************************************/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdevcfg_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdevcfg_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdmaps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdmaps.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdmaps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdmaps.h
index e0a283600..5a0c1a28e 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdmaps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdmaps.h
@@ -33,7 +33,7 @@
/**
*
* @file xdmaps.h
-* @addtogroup dmaps_v2_1
+* @addtogroup dmaps_v2_3
* @{
* @details
*
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdmaps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdmaps_hw.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdmaps_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdmaps_hw.h
index 1186107ac..628f1ec4f 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdmaps_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xdmaps_hw.h
@@ -33,7 +33,7 @@
/**
*
* @file xdmaps_hw.h
-* @addtogroup dmaps_v2_1
+* @addtogroup dmaps_v2_3
* @{
*
* This header file contains the hardware interface of an XDmaPs device.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps.h
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps.h
index 1dbdbb20d..6d4b15b24 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps.h
@@ -33,7 +33,7 @@
/**
*
* @file xemacps.h
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
* @{
* @details
*
@@ -322,6 +322,15 @@
* for CR-965028.
* ms 03/17/17 Modified text file in examples folder for doxygen
* generation.
+ * ms 04/05/17 Added tabspace for return statements in functions of
+ * xemacps_ieee1588_example.c for proper documentation
+ * while generating doxygen.
+ * 3.5 hk 08/14/17 Update cache coherency information of the interface in
+ * its config structure.
+ * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+ * changed to volatile.
+ * Add API XEmacPs_BdRingPtrReset() to reset pointers
+ *
* </pre>
*
****************************************************************************/
@@ -519,6 +528,8 @@ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
typedef struct {
u16 DeviceId; /**< Unique ID of device */
UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
+ u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
+ * describes whether Cache Coherent or not */
} XEmacPs_Config;
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bd.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_bd.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bd.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_bd.h
index 52c5f7e7e..83f9a87fc 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bd.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_bd.h
@@ -33,7 +33,7 @@
/**
*
* @file xemacps_bd.h
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
* @{
*
* This header provides operations to manage buffer descriptors in support
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bdring.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_bdring.h
similarity index 97%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bdring.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_bdring.h
index de78cf28f..b89e89885 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bdring.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_bdring.h
@@ -33,7 +33,7 @@
/**
*
* @file xemacps_bdring.h
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
* @{
*
* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
@@ -47,6 +47,8 @@
* 1.00a wsy 01/10/10 First release
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+* changed to volatile.
*
* </pre>
*
@@ -81,7 +83,7 @@ typedef struct {
XEmacPs_Bd *BdaRestart;
/**< BDA to load when channel is started */
- u32 HwCnt; /**< Number of BDs in work group */
+ volatile u32 HwCnt; /**< Number of BDs in work group */
u32 PreCnt; /**< Number of BDs in pre-work group */
u32 FreeCnt; /**< Number of allocatable BDs in the free group */
u32 PostCnt; /**< Number of BDs in post-work group */
@@ -228,6 +230,7 @@ u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
XEmacPs_Bd ** BdSetPtr);
LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
#ifdef __cplusplus
}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_hw.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_hw.h
index 953cc6265..e535470c2 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xemacps_hw.h
@@ -33,7 +33,7 @@
/**
*
* @file xemacps_hw.h
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
* @{
*
* This header file contains identifiers and low-level driver functions (or
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xenv.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xenv.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xenv.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xenv.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xenv_standalone.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xenv_standalone.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xenv_standalone.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xenv_standalone.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpio.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpio.h
index fc3f0bd33..582d94a76 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpio.h
@@ -32,7 +32,7 @@
/*****************************************************************************/
/**
* @file xgpio.h
-* @addtogroup gpio_v4_2
+* @addtogroup gpio_v4_3
* @{
* @details
*
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_l.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpio_l.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_l.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpio_l.h
index 9c88aba2e..153fdfdf1 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_l.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpio_l.h
@@ -33,7 +33,7 @@
/**
*
* @file xgpio_l.h
-* @addtogroup gpio_v4_2
+* @addtogroup gpio_v4_3
* @{
*
* This header file contains identifiers and driver functions (or
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpiops.h
similarity index 95%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpiops.h
index 367380656..fda562d91 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpiops.h
@@ -1,3 +1,4 @@
+
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
@@ -33,7 +34,7 @@
/**
*
* @file xgpiops.h
-* @addtogroup gpiops_v3_1
+* @addtogroup gpiops_v3_3
* @{
* @details
*
@@ -99,7 +100,13 @@
* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
-*
+* ms 04/05/17 Added tabspace for return statements in functions of
+* gpiops examples for proper documentation while
+* generating doxygen.
+* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
+* for zcu102 and zc702 boards in polled and interrupt
+* example, configured Interrupt pin to input pin for
+* proper functioning of interrupt example.
* </pre>
*
******************************************************************************/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpiops_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpiops_hw.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpiops_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpiops_hw.h
index 81e8d6a9f..ff0190675 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpiops_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xgpiops_hw.h
@@ -33,7 +33,7 @@
/**
*
* @file xgpiops_hw.h
-* @addtogroup gpiops_v3_1
+* @addtogroup gpiops_v3_3
* @{
*
* This header file contains the identifiers and basic driver functions (or
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xiicps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xiicps.h
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xiicps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xiicps.h
index a7b956f64..d3713de47 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xiicps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xiicps.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xiicps.h
-* @addtogroup iicps_v3_0
+* @addtogroup iicps_v3_7
* @{
* @details
*
@@ -186,6 +186,8 @@
* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
+* 3.7 ask 04/17/18 Updated the Eeprom scanning mechanism
+* as per the other examples (CR#997545)
*
* </pre>
*
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xiicps_hw.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xiicps_hw.h
index 3b00cf8b1..e9d63ec8f 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xiicps_hw.h
@@ -33,7 +33,7 @@
/**
*
* @file xiicps_hw.h
-* @addtogroup iicps_v3_0
+* @addtogroup iicps_v3_7
* @{
*
* This header file contains the hardware definition for an IIC device.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_assert.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_assert.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_assert.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_assert.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_cache.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_cache.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_cache.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_cache.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_cache_l.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_cache_l.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_cache_l.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_cache_l.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_cache_vxworks.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_cache_vxworks.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_errata.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_errata.h
similarity index 96%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_errata.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_errata.h
index 800fcd562..490aebeab 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_errata.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_errata.h
@@ -52,6 +52,7 @@
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a srt 04/18/13 First release
+* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
* </pre>
*
******************************************************************************/
@@ -113,15 +114,10 @@
*/
#define CONFIG_PL310_ERRATA_727915 1
-/**
- * Errata No: 753970
- * Description: Cache sync operation may be faulty
- */
-#define CONFIG_PL310_ERRATA_753970 1
/*@}*/
#endif /* ENABLE_ARM_ERRATA */
#endif /* XIL_ERRATA_H */
/**
* @} End of "addtogroup a9_errata".
-*/
\ No newline at end of file
+*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_exception.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_exception.h
similarity index 97%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_exception.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_exception.h
index ad4822205..83303875d 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_exception.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_exception.h
@@ -51,6 +51,8 @@
* ----- -------- -------- -----------------------------------------------
* 5.2 pkp 28/05/15 First release
* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
+* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
+* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
* </pre>
*
******************************************************************************/
@@ -235,6 +237,8 @@ extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
void *Data);
extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler *Handler, void **Data);
extern void Xil_ExceptionInit(void);
#if defined (__aarch64__)
@@ -253,4 +257,4 @@ extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
#endif /* XIL_EXCEPTION_H */
/**
* @} End of "addtogroup arm_exception_apis".
-*/
\ No newline at end of file
+*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_hal.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_hal.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_hal.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_hal.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_io.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_io.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_io.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_io.h
index 99bf4d05d..9c5aa43c7 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_io.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_io.h
@@ -303,7 +303,7 @@ static INLINE u32 Xil_In32LE(UINTPTR Addr)
static INLINE u32 Xil_In32BE(UINTPTR Addr)
#endif
{
- u16 value = Xil_In32(Addr);
+ u32 value = Xil_In32(Addr);
return Xil_EndianSwap32(value);
}
@@ -342,4 +342,4 @@ static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_io_interfacing_apis".
-*/
\ No newline at end of file
+*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_macroback.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_macroback.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_macroback.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_macroback.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_mem.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_mem.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_mem.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_mem.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_misc_psreset_api.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_misc_psreset_api.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_mmu.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_mmu.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_mmu.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_mmu.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_printf.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_printf.h
similarity index 91%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_printf.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_printf.h
index 2be5c5734..016ae3b2f 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_printf.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_printf.h
@@ -10,6 +10,10 @@ extern "C" {
#include <stdarg.h>
#include "xil_types.h"
#include "xparameters.h"
+#include "bspconfig.h"
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+#include "xen_console.h"
+#endif
/*----------------------------------------------------*/
/* Use the following parameter passing structure to */
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h
new file mode 100644
index 000000000..4bfac0ac4
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
+* For sleep related functions that can be used across all Xilinx supported
+* processors, please use xil_sleeptimer.h.
+*
+*
+* <pre>
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 10/18/17 First Release.
+*
+* </pre>
+*****************************************************************************/
+
+#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */
+#define XIL_SLEEPTIMER_H /* by using protection macros */
+/**************************** Include Files ********************************/
+
+#include "xil_io.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+
+/************************** Constant Definitions *****************************/
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#define XSLEEP_TIMER_REG_SHIFT 32U
+#define XSleep_ReadCounterVal Xil_In32
+#define XCntrVal u32
+#else
+#define XSLEEP_TIMER_REG_SHIFT 16U
+#define XSleep_ReadCounterVal Xil_In16
+#define XCntrVal u16
+#endif
+
+#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
+#define RST_LPD_IOU2 0xFF5E0238U
+#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U
+#endif
+
+#if defined (SLEEP_TIMER_BASEADDR)
+/** @name Register Map
+*
+* Register offsets from the base address of the TTC device
+*
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U
+ /**< Clock Control Register */
+ #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU
+ /**< Counter Control Register*/
+ #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U
+ /**< Current Counter Value */
+/* @} */
+/** @name Clock Control Register
+* Clock Control Register definitions of TTC
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U
+ /**< Prescale enable */
+/* @} */
+/** @name Counter Control Register
+* Counter Control Register definitions of TTC
+* @{
+*/
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U
+ /**< Disable the counter */
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U
+ /**< Reset counter */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SleepTTCCommon(u32 delay, u64 frequency);
+void XTime_StartTTCTimer();
+
+#endif
+#endif /* XIL_SLEEPTIMER_H */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_testcache.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_testcache.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_testcache.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_testcache.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_testio.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_testio.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_testio.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_testio.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_testmem.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_testmem.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_testmem.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_testmem.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_types.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_types.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_types.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xil_types.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xl2cc.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xl2cc.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xl2cc.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xl2cc.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xl2cc_counter.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xl2cc_counter.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xl2cc_counter.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xl2cc_counter.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xparameters.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xparameters.h
similarity index 81%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xparameters.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xparameters.h
index 85419e8c5..6599c095d 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xparameters.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xparameters.h
@@ -2,16 +2,16 @@
#define XPARAMETERS_H /* by using protection macros */
/* Definition for CPU ID */
-#define XPAR_CPU_ID 0
+#define XPAR_CPU_ID 0U
/* Definitions for peripheral PS7_CORTEXA9_0 */
-#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 650000000
+#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
/******************************************************************/
/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
-#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 650000000
+#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
/******************************************************************/
@@ -23,29 +23,37 @@
/******************************************************************/
+/* Platform specific definitions */
+#define PLATFORM_ZYNQ
+
+/* Definitions for sleep timer configuration */
+#define XSLEEP_TIMER_IS_DEFAULT_TIMER
+
+
+/******************************************************************/
/* Definitions for peripheral PS7_DDR_0 */
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
-#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF
+#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
/******************************************************************/
/* Definitions for driver DEVCFG */
-#define XPAR_XDCFG_NUM_INSTANCES 1
+#define XPAR_XDCFG_NUM_INSTANCES 1U
/* Definitions for peripheral PS7_DEV_CFG_0 */
-#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0
-#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000
-#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF
+#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U
+#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U
+#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU
/******************************************************************/
/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
-#define XPAR_XDCFG_0_BASEADDR 0xF8007000
-#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF
+#define XPAR_XDCFG_0_BASEADDR 0xF8007000U
+#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU
/******************************************************************/
@@ -94,10 +102,12 @@
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50
+#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0
/******************************************************************/
+#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0
/* Canonical definitions for peripheral PS7_ETHERNET_0 */
#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
#define XPAR_XEMACPS_0_BASEADDR 0xE000B000
@@ -109,6 +119,7 @@
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50
+#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0
/******************************************************************/
@@ -209,14 +220,14 @@
/******************************************************************/
/* Definitions for driver GPIO */
-#define XPAR_XGPIO_NUM_INSTANCES 2
+#define XPAR_XGPIO_NUM_INSTANCES 4
/* Definitions for peripheral AXI_GPIO_0 */
#define XPAR_AXI_GPIO_0_BASEADDR 0x41200000
#define XPAR_AXI_GPIO_0_HIGHADDR 0x4120FFFF
#define XPAR_AXI_GPIO_0_DEVICE_ID 0
#define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_AXI_GPIO_0_IS_DUAL 1
+#define XPAR_AXI_GPIO_0_IS_DUAL 0
/* Definitions for peripheral AXI_GPIO_1 */
@@ -227,6 +238,22 @@
#define XPAR_AXI_GPIO_1_IS_DUAL 0
+/* Definitions for peripheral AXI_GPIO_2 */
+#define XPAR_AXI_GPIO_2_BASEADDR 0x41220000
+#define XPAR_AXI_GPIO_2_HIGHADDR 0x4122FFFF
+#define XPAR_AXI_GPIO_2_DEVICE_ID 2
+#define XPAR_AXI_GPIO_2_INTERRUPT_PRESENT 0
+#define XPAR_AXI_GPIO_2_IS_DUAL 0
+
+
+/* Definitions for peripheral AXI_GPIO_3 */
+#define XPAR_AXI_GPIO_3_BASEADDR 0x41230000
+#define XPAR_AXI_GPIO_3_HIGHADDR 0x4123FFFF
+#define XPAR_AXI_GPIO_3_DEVICE_ID 3
+#define XPAR_AXI_GPIO_3_INTERRUPT_PRESENT 0
+#define XPAR_AXI_GPIO_3_IS_DUAL 0
+
+
/******************************************************************/
/* Canonical definitions for peripheral AXI_GPIO_0 */
@@ -234,7 +261,7 @@
#define XPAR_GPIO_0_HIGHADDR 0x4120FFFF
#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
#define XPAR_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_0_IS_DUAL 1
+#define XPAR_GPIO_0_IS_DUAL 0
/* Canonical definitions for peripheral AXI_GPIO_1 */
#define XPAR_GPIO_1_BASEADDR 0x41210000
@@ -243,6 +270,20 @@
#define XPAR_GPIO_1_INTERRUPT_PRESENT 0
#define XPAR_GPIO_1_IS_DUAL 0
+/* Canonical definitions for peripheral AXI_GPIO_2 */
+#define XPAR_GPIO_2_BASEADDR 0x41220000
+#define XPAR_GPIO_2_HIGHADDR 0x4122FFFF
+#define XPAR_GPIO_2_DEVICE_ID XPAR_AXI_GPIO_2_DEVICE_ID
+#define XPAR_GPIO_2_INTERRUPT_PRESENT 0
+#define XPAR_GPIO_2_IS_DUAL 0
+
+/* Canonical definitions for peripheral AXI_GPIO_3 */
+#define XPAR_GPIO_3_BASEADDR 0x41230000
+#define XPAR_GPIO_3_HIGHADDR 0x4123FFFF
+#define XPAR_GPIO_3_DEVICE_ID XPAR_AXI_GPIO_3_DEVICE_ID
+#define XPAR_GPIO_3_INTERRUPT_PRESENT 0
+#define XPAR_GPIO_3_IS_DUAL 0
+
/******************************************************************/
@@ -272,14 +313,14 @@
#define XPAR_PS7_I2C_0_DEVICE_ID 0
#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
-#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 108333336
+#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
/* Definitions for peripheral PS7_I2C_1 */
#define XPAR_PS7_I2C_1_DEVICE_ID 1
#define XPAR_PS7_I2C_1_BASEADDR 0xE0005000
#define XPAR_PS7_I2C_1_HIGHADDR 0xE0005FFF
-#define XPAR_PS7_I2C_1_I2C_CLK_FREQ_HZ 108333336
+#define XPAR_PS7_I2C_1_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/
@@ -288,13 +329,13 @@
#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
#define XPAR_XIICPS_0_BASEADDR 0xE0004000
#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
-#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 108333336
+#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
/* Canonical definitions for peripheral PS7_I2C_1 */
#define XPAR_XIICPS_1_DEVICE_ID XPAR_PS7_I2C_1_DEVICE_ID
#define XPAR_XIICPS_1_BASEADDR 0xE0005000
#define XPAR_XIICPS_1_HIGHADDR 0xE0005FFF
-#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 108333336
+#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/
@@ -304,38 +345,38 @@
/* Definitions for peripheral PWM_RECORDER_0 */
#define XPAR_PWM_RECORDER_0_DEVICE_ID 0
-#define XPAR_PWM_RECORDER_0_S_AXI_BASEADDR 0x43C40000
-#define XPAR_PWM_RECORDER_0_S_AXI_HIGHADDR 0x43C4FFFF
+#define XPAR_PWM_RECORDER_0_S_AXI_BASEADDR 0x76EA0000
+#define XPAR_PWM_RECORDER_0_S_AXI_HIGHADDR 0x76EAFFFF
/* Definitions for peripheral PWM_RECORDER_1 */
#define XPAR_PWM_RECORDER_1_DEVICE_ID 1
-#define XPAR_PWM_RECORDER_1_S_AXI_BASEADDR 0x43C50000
-#define XPAR_PWM_RECORDER_1_S_AXI_HIGHADDR 0x43C5FFFF
+#define XPAR_PWM_RECORDER_1_S_AXI_BASEADDR 0x76E80000
+#define XPAR_PWM_RECORDER_1_S_AXI_HIGHADDR 0x76E8FFFF
/* Definitions for peripheral PWM_RECORDER_2 */
#define XPAR_PWM_RECORDER_2_DEVICE_ID 2
-#define XPAR_PWM_RECORDER_2_S_AXI_BASEADDR 0x43C60000
-#define XPAR_PWM_RECORDER_2_S_AXI_HIGHADDR 0x43C6FFFF
+#define XPAR_PWM_RECORDER_2_S_AXI_BASEADDR 0x76E60000
+#define XPAR_PWM_RECORDER_2_S_AXI_HIGHADDR 0x76E6FFFF
/* Definitions for peripheral PWM_RECORDER_3 */
#define XPAR_PWM_RECORDER_3_DEVICE_ID 3
-#define XPAR_PWM_RECORDER_3_S_AXI_BASEADDR 0x43C70000
-#define XPAR_PWM_RECORDER_3_S_AXI_HIGHADDR 0x43C7FFFF
+#define XPAR_PWM_RECORDER_3_S_AXI_BASEADDR 0x76E40000
+#define XPAR_PWM_RECORDER_3_S_AXI_HIGHADDR 0x76E4FFFF
/* Definitions for peripheral PWM_RECORDER_4 */
#define XPAR_PWM_RECORDER_4_DEVICE_ID 4
-#define XPAR_PWM_RECORDER_4_S_AXI_BASEADDR 0x43C80000
-#define XPAR_PWM_RECORDER_4_S_AXI_HIGHADDR 0x43C8FFFF
+#define XPAR_PWM_RECORDER_4_S_AXI_BASEADDR 0x76E20000
+#define XPAR_PWM_RECORDER_4_S_AXI_HIGHADDR 0x76E2FFFF
/* Definitions for peripheral PWM_RECORDER_5 */
#define XPAR_PWM_RECORDER_5_DEVICE_ID 5
-#define XPAR_PWM_RECORDER_5_S_AXI_BASEADDR 0x43C90000
-#define XPAR_PWM_RECORDER_5_S_AXI_HIGHADDR 0x43C9FFFF
+#define XPAR_PWM_RECORDER_5_S_AXI_BASEADDR 0x76E00000
+#define XPAR_PWM_RECORDER_5_S_AXI_HIGHADDR 0x76E0FFFF
/******************************************************************/
@@ -345,26 +386,26 @@
/* Definitions for peripheral PWM_SIGNAL_OUT_0 */
#define XPAR_PWM_SIGNAL_OUT_0_DEVICE_ID 0
-#define XPAR_PWM_SIGNAL_OUT_0_S_AXI_BASEADDR 0x43C00000
-#define XPAR_PWM_SIGNAL_OUT_0_S_AXI_HIGHADDR 0x43C0FFFF
+#define XPAR_PWM_SIGNAL_OUT_0_S_AXI_BASEADDR 0x79460000
+#define XPAR_PWM_SIGNAL_OUT_0_S_AXI_HIGHADDR 0x7946FFFF
/* Definitions for peripheral PWM_SIGNAL_OUT_1 */
#define XPAR_PWM_SIGNAL_OUT_1_DEVICE_ID 1
-#define XPAR_PWM_SIGNAL_OUT_1_S_AXI_BASEADDR 0x43C10000
-#define XPAR_PWM_SIGNAL_OUT_1_S_AXI_HIGHADDR 0x43C1FFFF
+#define XPAR_PWM_SIGNAL_OUT_1_S_AXI_BASEADDR 0x79440000
+#define XPAR_PWM_SIGNAL_OUT_1_S_AXI_HIGHADDR 0x7944FFFF
/* Definitions for peripheral PWM_SIGNAL_OUT_2 */
#define XPAR_PWM_SIGNAL_OUT_2_DEVICE_ID 2
-#define XPAR_PWM_SIGNAL_OUT_2_S_AXI_BASEADDR 0x43C20000
-#define XPAR_PWM_SIGNAL_OUT_2_S_AXI_HIGHADDR 0x43C2FFFF
+#define XPAR_PWM_SIGNAL_OUT_2_S_AXI_BASEADDR 0x79420000
+#define XPAR_PWM_SIGNAL_OUT_2_S_AXI_HIGHADDR 0x7942FFFF
/* Definitions for peripheral PWM_SIGNAL_OUT_3 */
#define XPAR_PWM_SIGNAL_OUT_3_DEVICE_ID 3
-#define XPAR_PWM_SIGNAL_OUT_3_S_AXI_BASEADDR 0x43C30000
-#define XPAR_PWM_SIGNAL_OUT_3_S_AXI_HIGHADDR 0x43C3FFFF
+#define XPAR_PWM_SIGNAL_OUT_3_S_AXI_BASEADDR 0x79400000
+#define XPAR_PWM_SIGNAL_OUT_3_S_AXI_HIGHADDR 0x7940FFFF
/******************************************************************/
@@ -378,6 +419,7 @@
#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
#define XPAR_PS7_QSPI_0_QSPI_MODE 0
+#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2
/******************************************************************/
@@ -388,27 +430,28 @@
#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
#define XPAR_XQSPIPS_0_QSPI_MODE 0
+#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2
/******************************************************************/
/* Definitions for driver SCUGIC */
-#define XPAR_XSCUGIC_NUM_INSTANCES 1
+#define XPAR_XSCUGIC_NUM_INSTANCES 1U
/* Definitions for peripheral PS7_SCUGIC_0 */
-#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0
-#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100
-#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF
-#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000
+#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U
+#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U
+#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU
+#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
/******************************************************************/
/* Canonical definitions for peripheral PS7_SCUGIC_0 */
-#define XPAR_SCUGIC_0_DEVICE_ID 0
-#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100
-#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF
-#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000
+#define XPAR_SCUGIC_0_DEVICE_ID 0U
+#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U
+#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU
+#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
/******************************************************************/
@@ -460,7 +503,7 @@
#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
#define XPAR_PS7_SD_0_HAS_CD 1
-#define XPAR_PS7_SD_0_HAS_WP 1
+#define XPAR_PS7_SD_0_HAS_WP 0
#define XPAR_PS7_SD_0_BUS_WIDTH 0
#define XPAR_PS7_SD_0_MIO_BANK 0
#define XPAR_PS7_SD_0_HAS_EMIO 0
@@ -468,57 +511,19 @@
/******************************************************************/
+#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0
/* Canonical definitions for peripheral PS7_SD_0 */
#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
#define XPAR_XSDPS_0_BASEADDR 0xE0100000
#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
#define XPAR_XSDPS_0_HAS_CD 1
-#define XPAR_XSDPS_0_HAS_WP 1
+#define XPAR_XSDPS_0_HAS_WP 0
#define XPAR_XSDPS_0_BUS_WIDTH 0
#define XPAR_XSDPS_0_MIO_BANK 0
#define XPAR_XSDPS_0_HAS_EMIO 0
-/******************************************************************/
-
-/* Definitions for driver TTCPS */
-#define XPAR_XTTCPS_NUM_INSTANCES 3
-
-/* Definitions for peripheral PS7_TTC_0 */
-#define XPAR_PS7_TTC_0_DEVICE_ID 0
-#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000
-#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 108333336
-#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0
-#define XPAR_PS7_TTC_1_DEVICE_ID 1
-#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004
-#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 108333336
-#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0
-#define XPAR_PS7_TTC_2_DEVICE_ID 2
-#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008
-#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 108333336
-#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_TTC_0 */
-#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID
-#define XPAR_XTTCPS_0_BASEADDR 0xF8001000
-#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 108333336
-#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0
-
-#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID
-#define XPAR_XTTCPS_1_BASEADDR 0xF8001004
-#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 108333336
-#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0
-
-#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID
-#define XPAR_XTTCPS_2_BASEADDR 0xF8001008
-#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 108333336
-#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0
-
-
/******************************************************************/
/* Definitions for driver UARTPS */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xparameters_ps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xparameters_ps.h
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xparameters_ps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xparameters_ps.h
index ea0d2bcde..0fa77710d 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xparameters_ps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xparameters_ps.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -45,6 +45,8 @@
* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
* driver tcl
* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
+* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
+*
* </pre>
*
* @note
@@ -60,6 +62,9 @@
extern "C" {
#endif
+/**************************** Include Files *******************************/
+
+
/************************** Constant Definitions *****************************/
/*
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xplatform_info.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xplatform_info.h
similarity index 88%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xplatform_info.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xplatform_info.h
index 27c0b5851..0582222bc 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xplatform_info.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xplatform_info.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -41,6 +41,15 @@
* platform information.
*
* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- --------- -------------------------------------------------------
+* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+* function for PMUFW.
+* </pre>
+*
******************************************************************************/
#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
@@ -70,6 +79,7 @@ extern "C" {
#define XPS_VERSION_2 0x1
#define XPLAT_INFO_MASK (0xF)
+#define XPLAT_INFO_SHIFT (0xC)
#define XPS_VERSION_INFO_MASK (0xF)
/**************************** Type Definitions *******************************/
@@ -79,7 +89,7 @@ extern "C" {
u32 XGetPlatform_Info();
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
u32 XGetPSVersion_Info();
#endif
@@ -96,4 +106,4 @@ u32 XGet_Zynq_UltraMp_Platform_info();
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_platform_info".
-*/
\ No newline at end of file
+*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xpm_counter.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xpm_counter.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xpm_counter.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xpm_counter.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xpseudo_asm.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xpseudo_asm.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xpseudo_asm.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xpseudo_asm.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpseudo_asm_gcc.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
similarity index 96%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpseudo_asm_gcc.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
index 1b6726394..37971bc59 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpseudo_asm_gcc.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
@@ -120,6 +120,13 @@ extern "C" {
rval;\
})
+#define mfelrel3() ({u64 rval = 0U; \
+ asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v))
+
#else
/* pseudo assembler instructions */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xqspips.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xqspips.h
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xqspips.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xqspips.h
index 671f3f636..139ce4d38 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xqspips.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xqspips.h
@@ -33,7 +33,7 @@
/**
*
* @file xqspips.h
-* @addtogroup qspips_v3_2
+* @addtogroup qspips_v3_4
* @{
* @details
*
@@ -275,6 +275,12 @@
* to remove compilation warnings. CR# 868893.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
+* ms 04/05/17 Modified Comment lines in functions of qspips
+* examples to recognize it as documentation block
+* and modified filename tag in
+* xqspips_dual_flash_stack_lqspi_example.c to include it in
+* doxygen examples.
+* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
*
* </pre>
*
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xqspips_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xqspips_hw.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xqspips_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xqspips_hw.h
index 404afed94..96c867ad3 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xqspips_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xqspips_hw.h
@@ -33,7 +33,7 @@
/**
*
* @file xqspips_hw.h
-* @addtogroup qspips_v3_2
+* @addtogroup qspips_v3_4
* @{
*
* This header file contains the identifiers and basic HW access driver
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xreg_cortexa9.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xreg_cortexa9.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscugic.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscugic.h
similarity index 92%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscugic.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscugic.h
index fb6624239..e22ee5bc2 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscugic.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscugic.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xscugic.h
-* @addtogroup scugic_v3_1
+* @addtogroup scugic_v3_8
* @{
* @details
*
@@ -166,6 +166,19 @@
* XScugiC_GetCpuId to access CpuId.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
+* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro
+* definitions of scugic in xparameters.h
+* 3.8 mus 07/05/17 Updated scugic.tcl to add support for intrrupts connected
+* through util_reduced_vector IP(OR gate)
+* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
+* the HandlerTable in XScuGic_ConfigTable to 0, it removes
+* the compilation warning in xscugic_g.c. Fix for CR#978736.
+* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical
+* definitions for pl to ps interrupts.Fix for CR#980534
+* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
+* XScuGic_InterruptUnmapFromCpu, These API's can be used
+* by applications to unmap specific/all interrupts from
+* target CPU.
*
* </pre>
*
@@ -331,6 +344,8 @@ void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
u8 Priority, u8 Trigger);
void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id);
void XScuGic_Stop(XScuGic *InstancePtr);
void XScuGic_SetCpuID(u32 CpuCoreId);
u32 XScuGic_GetCpuID(void);
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscugic_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscugic_hw.h
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscugic_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscugic_hw.h
index 5eaa633e3..08e65f456 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscugic_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscugic_hw.h
@@ -33,7 +33,7 @@
/**
*
* @file xscugic_hw.h
-* @addtogroup scugic_v3_1
+* @addtogroup scugic_v3_8
* @{
*
* This header file contains identifiers and HW access functions (or
@@ -72,6 +72,10 @@
* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
+* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
+* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
+* API's can be used by applications to unmap specific/all
+* interrupts from target CPU. It fixes CR#992490.
* </pre>
*
******************************************************************************/
@@ -633,6 +637,10 @@ void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
u8 Priority, u8 Trigger);
void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
u8 *Priority, u8 *Trigger);
+void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscutimer.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscutimer.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscutimer.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscutimer.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscutimer_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscutimer_hw.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscutimer_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscutimer_hw.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscuwdt.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscuwdt.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscuwdt.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscuwdt.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscuwdt_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscuwdt_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xsdps.h
similarity index 94%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xsdps.h
index 9e475207d..b8d979d1d 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xsdps.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xsdps.h
-* @addtogroup sdps_v2_5
+* @addtogroup sdps_v3_5
* @{
* @details
*
@@ -144,6 +144,11 @@
* sk 02/01/17 Consider bus width parameter from design for switching
* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
* sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
+* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
+* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
+* information.
+* mn 09/06/17 Resolved compilation errors with IAR toolchain
*
* </pre>
*
@@ -161,6 +166,7 @@ extern "C" {
#include "xil_cache.h"
#include "xstatus.h"
#include "xsdps_hw.h"
+#include "xplatform_info.h"
#include <string.h>
/************************** Constant Definitions *****************************/
@@ -184,14 +190,25 @@ typedef struct {
u32 BusWidth; /**< Bus Width */
u32 BankNumber; /**< MIO Bank selection for SD */
u32 HasEMIO; /**< If SD is connected to EMIO */
+ u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
} XSdPs_Config;
/* ADMA2 descriptor table */
typedef struct {
u16 Attribute; /**< Attributes of descriptor */
u16 Length; /**< Length of current dma transfer */
+#ifdef __aarch64__
+ u64 Address; /**< Address of current dma transfer */
+#else
u32 Address; /**< Address of current dma transfer */
+#endif
+#ifdef __ICCARM__
+#pragma data_alignment = 32
} XSdPs_Adma2Descriptor;
+#pragma data_alignment = 4
+#else
+} __attribute__((__packed__))XSdPs_Adma2Descriptor;
+#endif
/**
* The XSdPs driver instance data. The user is required to allocate a
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xsdps_hw.h
similarity index 96%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xsdps_hw.h
index 6bb6c2a61..c63d8f62a 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xsdps_hw.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xsdps_hw.h
-* @addtogroup sdps_v2_5
+* @addtogroup sdps_v3_5
* @{
*
* This header file contains the identifiers and basic HW access driver
@@ -57,6 +57,10 @@
* operating modes.
* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
* 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 08/22/17 Updated for Word Access System support
+* mn 09/06/17 Added support for ARMCC toolchain
+* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
+*
* </pre>
*
******************************************************************************/
@@ -995,6 +999,13 @@ extern "C" {
#define XSDPS_SD_SDR50_MAX_CLK 100000000U
#define XSDPS_SD_DDR50_MAX_CLK 50000000U
#define XSDPS_SD_SDR104_MAX_CLK 208000000U
+/*
+ * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
+ * than the clock value coming from the core. This value is kept to safely
+ * switch to SDR104 mode if the SD card supports it.
+ */
+#define XSDPS_SD_INPUT_MAX_CLK 175000000U
+
#define XSDPS_MMC_HS200_MAX_CLK 200000000U
#define XSDPS_MMC_HSD_MAX_CLK 52000000U
#define XSDPS_MMC_DDR_MAX_CLK 52000000U
@@ -1163,8 +1174,18 @@ extern "C" {
* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
*
******************************************************************************/
-#define XSdPs_ReadReg16(BaseAddress, RegOffset) \
- XSdPs_In16((BaseAddress) + (RegOffset))
+static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u16)Reg;
+#else
+ return XSdPs_In16((BaseAddress) + (RegOffset));
+#endif
+}
/***************************************************************************/
/**
@@ -1182,8 +1203,20 @@ extern "C" {
* u16 RegisterValue)
*
******************************************************************************/
-#define XSdPs_WriteReg16(BaseAddress, RegOffset, RegisterValue) \
- XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue))
+
+static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
/****************************************************************************/
/**
@@ -1199,9 +1232,18 @@ extern "C" {
* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
*
******************************************************************************/
-#define XSdPs_ReadReg8(BaseAddress, RegOffset) \
- XSdPs_In8((BaseAddress) + (RegOffset))
-
+static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u8)Reg;
+#else
+ return XSdPs_In8((BaseAddress) + (RegOffset));
+#endif
+}
/***************************************************************************/
/**
* Write to a register.
@@ -1218,9 +1260,19 @@ extern "C" {
* u8 RegisterValue)
*
******************************************************************************/
-#define XSdPs_WriteReg8(BaseAddress, RegOffset, RegisterValue) \
- XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue))
-
+static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
/***************************************************************************/
/**
* Macro to get present status register
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xstatus.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xstatus.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xstatus.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xstatus.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xtime_l.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xtime_l.h
similarity index 90%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xtime_l.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xtime_l.h
index f939d84f6..9b872b6cb 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xtime_l.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xtime_l.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -48,6 +48,8 @@
* 3.06a sgd 05/15/12 Upadted get/set time functions to make use Global Timer
* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer
+* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
+* implementation
* </pre>
*
******************************************************************************/
@@ -76,9 +78,16 @@ typedef u64 XTime;
#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
#define GTIMER_CONTROL_OFFSET 0x08U
-
+#if defined (SLEEP_TIMER_BASEADDR)
+#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
+#else
/* Global Timer is always clocked at half of the CPU frequency */
#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
+#endif
+
+#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
+#pragma message ("For the sleep routines, Global timer is being used")
+#endif
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xuartps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xuartps.h
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xuartps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xuartps.h
index a5155940e..33758c23b 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xuartps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xuartps.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xuartps.h
-* @addtogroup uartps_v3_1
+* @addtogroup uartps_v3_5
* @{
* @details
*
@@ -168,6 +168,8 @@
* for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
+* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem
+* control register.
*
* </pre>
*
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xuartps_hw.h
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xuartps_hw.h
index 9f5f0b700..9a2bc4305 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xuartps_hw.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xuartps_hw.h
-* @addtogroup uartps_v3_1
+* @addtogroup uartps_v3_5
* @{
*
* This header file contains the hardware interface of an XUartPs device.
@@ -55,6 +55,8 @@
* constant definitions.
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+* 3.6 ms 02/16/18 Updates flow control mode offset value in
+* modem control register.
*
* </pre>
*
@@ -256,7 +258,7 @@ extern "C" {
*
* @{
*/
-#define XUARTPS_MODEMCR_FCM 0x00000010U /**< Flow control mode */
+#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
/* @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps.h
index 4a4492cdc..b5c472ef9 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps.h
@@ -33,7 +33,7 @@
/**
*
* @file xusbps.h
-* @addtogroup usbps_v2_2
+* @addtogroup usbps_v2_4
* @{
* @details
*
@@ -185,6 +185,8 @@
* 2.4 sg 04/26/16 Fixed CR#949693, Corrected the logic for EP flush
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
+ * ms 04/10/17 Modified filename tag to include the file in doxygen
+ * examples.
* </pre>
*
******************************************************************************/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h
index b8b9ad685..1cb0cfcd3 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h
@@ -33,7 +33,7 @@
/**
*
* @file xusbps_endpoint.h
-* @addtogroup usbps_v2_2
+* @addtogroup usbps_v2_4
* @{
*
* This is an internal file containung the definitions for endpoints. It is
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps_hw.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps_hw.h
index 792fbdde5..69f3ebffb 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/xusbps_hw.h
@@ -33,7 +33,7 @@
/**
*
* @file xusbps_hw.h
-* @addtogroup usbps_v2_2
+* @addtogroup usbps_v2_4
* @{
*
* This header file contains identifiers and low-level driver functions (or
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c
index cfa356ced..fca26ca2e 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c
@@ -33,7 +33,7 @@
/**
*
* @file xcoresightpsdcc.c
-* @addtogroup coresightps_dcc_v1_1
+* @addtogroup coresightps_dcc_v1_4
* @{
*
* Functions in this file are the minimum required functions for the
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xcoresightpsdcc.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xcoresightpsdcc.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h
index a732b235d..67959e327 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xcoresightpsdcc.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h
@@ -33,7 +33,7 @@
/**
*
* @file xcoresightpsdcc.h
-* @addtogroup coresightps_dcc_v1_1
+* @addtogroup coresightps_dcc_v1_4
* @{
* @details
*
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_4/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_4/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xcpu_cortexa9.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/xcpu_cortexa9.h
similarity index 86%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xcpu_cortexa9.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/xcpu_cortexa9.h
index 4d441e53e..95c8ba536 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xcpu_cortexa9.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/xcpu_cortexa9.h
@@ -33,11 +33,16 @@
/**
*
* @file xcpu_cortexa9.h
-* @addtogroup cpu_cortexa9_v2_1
+* @addtogroup cpu_cortexa9_v2_5
* @{
* @details
*
* dummy file
+* MODIFICATION HISTORY:
*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
+* parameter of cpu_cortexa9 in xparameters.h
******************************************************************************/
/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xddrps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
similarity index 96%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xddrps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
index fe7adb066..c8804d2ed 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xddrps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
@@ -18,8 +18,8 @@
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c
index dcb80303d..e9447e7e3 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c
@@ -33,7 +33,7 @@
/**
*
* @file xdevcfg.c
-* @addtogroup devcfg_v3_3
+* @addtogroup devcfg_v3_5
* @{
*
* This file contains the implementation of the interface functions for XDcfg
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdevcfg.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h
similarity index 97%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdevcfg.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h
index 7fc1332a5..b9a0111d6 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdevcfg.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xdevcfg.h
-* @addtogroup devcfg_v3_3
+* @addtogroup devcfg_v3_5
* @{
* @details
*
@@ -154,7 +154,11 @@
* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
-*
+* ms 04/10/17 Modified filename tag in interrupt and polled examples
+* to include them in doxygen examples.
+* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
+* definitions of devcfg in xparameters.h
+* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
* </pre>
*
******************************************************************************/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c
similarity index 96%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_g.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c
index 938489f6b..dc4228399 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_hw.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c
index 8a3095de3..bcb238f06 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_hw.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c
@@ -33,7 +33,7 @@
/**
*
* @file xdevcfg_hw.c
-* @addtogroup devcfg_v3_3
+* @addtogroup devcfg_v3_5
* @{
*
* This file contains the implementation of the interface reset functionality
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_intr.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c
index 55bbde2f0..b41b7ea37 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_intr.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c
@@ -33,7 +33,7 @@
/**
*
* @file xdevcfg_intr.c
-* @addtogroup devcfg_v3_3
+* @addtogroup devcfg_v3_5
* @{
*
* Contains the implementation of interrupt related functions of the XDcfg
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_selftest.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c
index 7159782e1..40cf1de6a 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_selftest.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c
@@ -33,7 +33,7 @@
/**
*
* @file xdevcfg_selftest.c
-* @addtogroup devcfg_v3_3
+* @addtogroup devcfg_v3_5
* @{
*
* Contains diagnostic self-test functions for the XDcfg driver.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c
similarity index 93%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_sinit.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c
index d0d0e6d99..bbc96a0c6 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_sinit.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xdevcfg_sinit.c
-* @addtogroup devcfg_v3_3
+* @addtogroup devcfg_v3_5
* @{
*
* This file contains method for static initialization (compile-time) of the
@@ -45,6 +45,7 @@
* Ver Who Date Changes
* ----- --- -------- ---------------------------------------------
* 1.00a hvm 02/07/11 First release
+* 3.5 ms 08/07/17 Fixed compilation warnings.
* </pre>
*
******************************************************************************/
@@ -79,9 +80,9 @@ XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId)
{
extern XDcfg_Config XDcfg_ConfigTable[];
XDcfg_Config *CfgPtr = NULL;
- int Index;
+ u32 Index;
- for (Index = 0; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) {
+ for (Index = 0U; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) {
if (XDcfg_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XDcfg_ConfigTable[Index];
break;
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c
index cb0d62a6f..9db769284 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c
@@ -33,7 +33,7 @@
/**
*
* @file xdmaps.c
-* @addtogroup dmaps_v2_1
+* @addtogroup dmaps_v2_3
* @{
*
* This file contains the implementation of the interface functions for XDmaPs
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h
index e0a283600..5a0c1a28e 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h
@@ -33,7 +33,7 @@
/**
*
* @file xdmaps.h
-* @addtogroup dmaps_v2_1
+* @addtogroup dmaps_v2_3
* @{
* @details
*
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c
similarity index 96%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c
index 00ed746e1..03b400a0b 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c
index 9fc3dd898..4c0cfbfd2 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c
@@ -33,7 +33,7 @@
/**
*
* @file xdmaps_hw.c
-* @addtogroup dmaps_v2_1
+* @addtogroup dmaps_v2_3
* @{
*
* This file contains the implementation of the interface reset functionality
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h
index 1186107ac..628f1ec4f 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h
@@ -33,7 +33,7 @@
/**
*
* @file xdmaps_hw.h
-* @addtogroup dmaps_v2_1
+* @addtogroup dmaps_v2_3
* @{
*
* This header file contains the hardware interface of an XDmaPs device.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c
index eae0846b5..daebd9903 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c
@@ -33,7 +33,7 @@
/**
*
* @file xdmaps_selftest.c
-* @addtogroup dmaps_v2_1
+* @addtogroup dmaps_v2_3
* @{
*
* This file contains the self-test functions for the XDmaPs driver.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c
index 20866cf57..b92ee5311 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c
@@ -33,7 +33,7 @@
/**
*
* @file xdmaps_sinit.c
-* @addtogroup dmaps_v2_1
+* @addtogroup dmaps_v2_3
* @{
*
* The implementation of the XDmaPs driver's static initialzation
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.c
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.c
index 26df03c3d..c013c4946 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.c
@@ -33,7 +33,7 @@
/**
*
* @file xemacps.c
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
* @{
*
* The XEmacPs driver. Functions in this file are the minimum required functions
@@ -52,6 +52,8 @@
* Disable extended mode. Perform all 64 bit changes under
* check for arch64.
* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr registers
+* 3.5 hk 08/14/17 Update cache coherency information of the interface in
+* its config structure.
*
* </pre>
******************************************************************************/
@@ -107,6 +109,7 @@ LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
/* Set device base address and ID */
InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
InstancePtr->Config.BaseAddress = EffectiveAddress;
+ InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
/* Set callbacks to an initial stub routine */
InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.h
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.h
index 1dbdbb20d..6d4b15b24 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.h
@@ -33,7 +33,7 @@
/**
*
* @file xemacps.h
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
* @{
* @details
*
@@ -322,6 +322,15 @@
* for CR-965028.
* ms 03/17/17 Modified text file in examples folder for doxygen
* generation.
+ * ms 04/05/17 Added tabspace for return statements in functions of
+ * xemacps_ieee1588_example.c for proper documentation
+ * while generating doxygen.
+ * 3.5 hk 08/14/17 Update cache coherency information of the interface in
+ * its config structure.
+ * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+ * changed to volatile.
+ * Add API XEmacPs_BdRingPtrReset() to reset pointers
+ *
* </pre>
*
****************************************************************************/
@@ -519,6 +528,8 @@ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
typedef struct {
u16 DeviceId; /**< Unique ID of device */
UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
+ u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
+ * describes whether Cache Coherent or not */
} XEmacPs_Config;
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_bd.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bd.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_bd.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bd.h
index 52c5f7e7e..83f9a87fc 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_bd.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bd.h
@@ -33,7 +33,7 @@
/**
*
* @file xemacps_bd.h
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
* @{
*
* This header provides operations to manage buffer descriptors in support
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bdring.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.c
similarity index 97%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bdring.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.c
index 7c539f448..3536873dc 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bdring.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.c
@@ -33,7 +33,7 @@
/**
*
* @file xemacps_bdring.c
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
* @{
*
* This file implements buffer descriptor ring related functions.
@@ -57,6 +57,8 @@
* from uncached area. Fix for CR #663885.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 rb 09/08/17 Add XEmacPs_BdRingPtrReset() API to reset BD ring
+* pointers
*
* </pre>
******************************************************************************/
@@ -1072,4 +1074,29 @@ static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
*TempPtr = DataValueTx;
}
}
+
+/*****************************************************************************/
+/**
+ * Reset BD ring head and tail pointers.
+ *
+ * @param RingPtr is the instance to be worked on.
+ * @param VirtAddr is the virtual base address of the user memory region.
+ *
+ * @note
+ * Should be called after XEmacPs_Stop()
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
+ *
+ *****************************************************************************/
+void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
+{
+ RingPtr->FreeHead = virtaddrloc;
+ RingPtr->PreHead = virtaddrloc;
+ RingPtr->HwHead = virtaddrloc;
+ RingPtr->HwTail = virtaddrloc;
+ RingPtr->PostHead = virtaddrloc;
+}
+
/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_bdring.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.h
similarity index 97%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_bdring.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.h
index de78cf28f..b89e89885 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_bdring.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.h
@@ -33,7 +33,7 @@
/**
*
* @file xemacps_bdring.h
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
* @{
*
* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
@@ -47,6 +47,8 @@
* 1.00a wsy 01/10/10 First release
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+* changed to volatile.
*
* </pre>
*
@@ -81,7 +83,7 @@ typedef struct {
XEmacPs_Bd *BdaRestart;
/**< BDA to load when channel is started */
- u32 HwCnt; /**< Number of BDs in work group */
+ volatile u32 HwCnt; /**< Number of BDs in work group */
u32 PreCnt; /**< Number of BDs in pre-work group */
u32 FreeCnt; /**< Number of allocatable BDs in the free group */
u32 PostCnt; /**< Number of BDs in post-work group */
@@ -228,6 +230,7 @@ u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
XEmacPs_Bd ** BdSetPtr);
LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
#ifdef __cplusplus
}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_control.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_control.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_control.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_control.c
index f52451a8c..8217a4521 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_control.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_control.c
@@ -33,7 +33,7 @@
/**
*
* @file xemacps_control.c
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
* @{
*
* Functions in this file implement general purpose command and control related
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c
similarity index 93%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_g.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c
index 081f9ed53..095bfd7a9 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@@ -48,7 +48,8 @@ XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] =
{
{
XPAR_PS7_ETHERNET_0_DEVICE_ID,
- XPAR_PS7_ETHERNET_0_BASEADDR
+ XPAR_PS7_ETHERNET_0_BASEADDR,
+ XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT
}
};
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_hw.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.c
index daba38397..00e79a58d 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_hw.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.c
@@ -33,7 +33,7 @@
/**
*
* @file xemacps_hw.c
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
* @{
*
* This file contains the implementation of the ethernet interface reset sequence
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.h
index 953cc6265..e535470c2 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.h
@@ -33,7 +33,7 @@
/**
*
* @file xemacps_hw.h
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
* @{
*
* This header file contains identifiers and low-level driver functions (or
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_intr.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_intr.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_intr.c
index 59636c4ef..9c355a163 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_intr.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_intr.c
@@ -33,7 +33,7 @@
/**
*
* @file xemacps_intr.c
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
* @{
*
* Functions in this file implement general purpose interrupt processing related
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_sinit.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_sinit.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_sinit.c
index 1bc5b3b19..e2d2078af 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_sinit.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_sinit.c
@@ -33,7 +33,7 @@
/**
*
* @file xemacps_sinit.c
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
* @{
*
* This file contains lookup method by device ID when success, it returns
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.c
index fe968c868..9b7210064 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.c
@@ -32,7 +32,7 @@
/*****************************************************************************/
/**
* @file xgpio.c
-* @addtogroup gpio_v4_2
+* @addtogroup gpio_v4_3
* @{
*
* The implementation of the XGpio driver's basic functionality. See xgpio.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpio.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpio.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.h
index fc3f0bd33..582d94a76 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpio.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.h
@@ -32,7 +32,7 @@
/*****************************************************************************/
/**
* @file xgpio.h
-* @addtogroup gpio_v4_2
+* @addtogroup gpio_v4_3
* @{
* @details
*
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_extra.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_extra.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_extra.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_extra.c
index 219952678..5ce0b58e9 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_extra.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_extra.c
@@ -32,7 +32,7 @@
/*****************************************************************************/
/**
* @file xgpio_extra.c
-* @addtogroup gpio_v4_2
+* @addtogroup gpio_v4_3
* @{
*
* The implementation of the XGpio driver's advanced discrete functions.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_g.c
similarity index 86%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_g.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_g.c
index 547585f78..57aa942dc 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@@ -57,6 +57,18 @@ XGpio_Config XGpio_ConfigTable[XPAR_XGPIO_NUM_INSTANCES] =
XPAR_AXI_GPIO_1_BASEADDR,
XPAR_AXI_GPIO_1_INTERRUPT_PRESENT,
XPAR_AXI_GPIO_1_IS_DUAL
+ },
+ {
+ XPAR_AXI_GPIO_2_DEVICE_ID,
+ XPAR_AXI_GPIO_2_BASEADDR,
+ XPAR_AXI_GPIO_2_INTERRUPT_PRESENT,
+ XPAR_AXI_GPIO_2_IS_DUAL
+ },
+ {
+ XPAR_AXI_GPIO_3_DEVICE_ID,
+ XPAR_AXI_GPIO_3_BASEADDR,
+ XPAR_AXI_GPIO_3_INTERRUPT_PRESENT,
+ XPAR_AXI_GPIO_3_IS_DUAL
}
};
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_i.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_i.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_i.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_i.h
index 50f59baa7..0e64915e9 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_i.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_i.h
@@ -32,7 +32,7 @@
/******************************************************************************/
/**
* @file xgpio_i.h
-* @addtogroup gpio_v4_2
+* @addtogroup gpio_v4_3
* @{
*
* This header file contains internal identifiers, which are those shared
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_intr.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_intr.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_intr.c
index 271bb765a..887932a2a 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_intr.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_intr.c
@@ -32,7 +32,7 @@
/*****************************************************************************/
/**
* @file xgpio_intr.c
-* @addtogroup gpio_v4_2
+* @addtogroup gpio_v4_3
* @{
*
* Implements GPIO interrupt processing functions for the XGpio driver.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpio_l.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_l.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpio_l.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_l.h
index 9c88aba2e..153fdfdf1 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpio_l.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_l.h
@@ -33,7 +33,7 @@
/**
*
* @file xgpio_l.h
-* @addtogroup gpio_v4_2
+* @addtogroup gpio_v4_3
* @{
*
* This header file contains identifiers and driver functions (or
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_selftest.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_selftest.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_selftest.c
index 77982e35d..8b1d75fe6 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_selftest.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_selftest.c
@@ -32,7 +32,7 @@
/*****************************************************************************/
/**
* @file xgpio_selftest.c
-* @addtogroup gpio_v4_2
+* @addtogroup gpio_v4_3
* @{
*
* The implementation of the XGpio driver's self test function.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_sinit.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_sinit.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_sinit.c
index e61de8412..4d825b3eb 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_sinit.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_sinit.c
@@ -32,7 +32,7 @@
/*****************************************************************************/
/**
* @file xgpio_sinit.c
-* @addtogroup gpio_v4_2
+* @addtogroup gpio_v4_3
* @{
*
* The implementation of the XGpio driver's static initialzation
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c
index 90eedb87d..7b6fe2e46 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c
@@ -33,7 +33,7 @@
/**
*
* @file xgpiops.c
-* @addtogroup gpiops_v3_1
+* @addtogroup gpiops_v3_3
* @{
*
* The XGpioPs driver. Functions in this file are the minimum required functions
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpiops.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h
similarity index 95%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpiops.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h
index 367380656..fda562d91 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpiops.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h
@@ -1,3 +1,4 @@
+
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
@@ -33,7 +34,7 @@
/**
*
* @file xgpiops.h
-* @addtogroup gpiops_v3_1
+* @addtogroup gpiops_v3_3
* @{
* @details
*
@@ -99,7 +100,13 @@
* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
-*
+* ms 04/05/17 Added tabspace for return statements in functions of
+* gpiops examples for proper documentation while
+* generating doxygen.
+* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
+* for zcu102 and zc702 boards in polled and interrupt
+* example, configured Interrupt pin to input pin for
+* proper functioning of interrupt example.
* </pre>
*
******************************************************************************/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c
similarity index 96%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_g.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c
index 44ac94fc5..1a24fb0d0 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_hw.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c
index d7a5e00f0..8961c4287 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_hw.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c
@@ -33,7 +33,7 @@
/**
*
* @file xgpiops_hw.c
-* @addtogroup gpiops_v3_1
+* @addtogroup gpiops_v3_3
* @{
*
* This file contains low level GPIO functions.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h
index 81e8d6a9f..ff0190675 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h
@@ -33,7 +33,7 @@
/**
*
* @file xgpiops_hw.h
-* @addtogroup gpiops_v3_1
+* @addtogroup gpiops_v3_3
* @{
*
* This header file contains the identifiers and basic driver functions (or
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_intr.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c
index f69a71828..a8b0a5626 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_intr.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c
@@ -33,7 +33,7 @@
/**
*
* @file xgpiops_intr.c
-* @addtogroup gpiops_v3_1
+* @addtogroup gpiops_v3_3
* @{
*
* This file contains functions related to GPIO interrupt handling.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_selftest.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c
index da1973a2d..378524c14 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_selftest.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c
@@ -33,7 +33,7 @@
/**
*
* @file xgpiops_selftest.c
-* @addtogroup gpiops_v3_1
+* @addtogroup gpiops_v3_3
* @{
*
* This file contains a diagnostic self-test function for the XGpioPs driver.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_sinit.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c
index 2ca008373..4cc0c390f 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_sinit.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c
@@ -33,7 +33,7 @@
/**
*
* @file xgpiops_sinit.c
-* @addtogroup gpiops_v3_1
+* @addtogroup gpiops_v3_3
* @{
*
* This file contains the implementation of the XGpioPs driver's static
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.c
index 1c6819152..9546b5490 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.c
@@ -33,7 +33,7 @@
/**
*
* @file xiicps.c
-* @addtogroup iicps_v3_0
+* @addtogroup iicps_v3_7
* @{
*
* Contains implementation of required functions for the XIicPs driver.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.h
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.h
index a7b956f64..d3713de47 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xiicps.h
-* @addtogroup iicps_v3_0
+* @addtogroup iicps_v3_7
* @{
* @details
*
@@ -186,6 +186,8 @@
* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
+* 3.7 ask 04/17/18 Updated the Eeprom scanning mechanism
+* as per the other examples (CR#997545)
*
* </pre>
*
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_g.c
similarity index 97%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_g.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_g.c
index f1fff951b..f98336c62 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_hw.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.c
index a1dba8e62..ce81d92ab 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_hw.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.c
@@ -33,7 +33,7 @@
/**
*
* @file xiicps_hw.c
-* @addtogroup iicps_v3_0
+* @addtogroup iicps_v3_7
* @{
*
* Contains implementation of required functions for providing the reset sequence
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xiicps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xiicps_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.h
index 3b00cf8b1..e9d63ec8f 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xiicps_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.h
@@ -33,7 +33,7 @@
/**
*
* @file xiicps_hw.h
-* @addtogroup iicps_v3_0
+* @addtogroup iicps_v3_7
* @{
*
* This header file contains the hardware definition for an IIC device.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_intr.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_intr.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_intr.c
index 5231049c7..6dccff4c8 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_intr.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_intr.c
@@ -33,7 +33,7 @@
/**
*
* @file xiicps_intr.c
-* @addtogroup iicps_v3_0
+* @addtogroup iicps_v3_7
* @{
*
* Contains functions of the XIicPs driver for interrupt-driven transfers.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_master.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_master.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_master.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_master.c
index 99890afaa..555420910 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_master.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_master.c
@@ -33,7 +33,7 @@
/**
*
* @file xiicps_master.c
-* @addtogroup iicps_v3_0
+* @addtogroup iicps_v3_7
* @{
*
* Handles master mode transfers.
@@ -63,7 +63,8 @@
* 02/18/15 Implemented larger data transfer using repeated start
* in Zynq UltraScale MP.
* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
-*
+* 3.6 ask 09/03/18 In XIicPs_MasterRecvPolled, set transfer size register
+* before slave address. Fix for CR996440.
* </pre>
*
******************************************************************************/
@@ -424,7 +425,6 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
- XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
/*
* Set up the transfer size register so the slave knows how much
@@ -440,6 +440,9 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
ByteCountVar);
}
+
+ XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
/*
* Intrs keeps all the error-related interrupts.
*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_options.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_options.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_options.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_options.c
index 1ebd78673..4ef69a1a0 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_options.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_options.c
@@ -33,7 +33,7 @@
/**
*
* @file xiicps_options.c
-* @addtogroup iicps_v3_0
+* @addtogroup iicps_v3_7
* @{
*
* Contains functions for the configuration of the XIccPs driver.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_selftest.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_selftest.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_selftest.c
index dd57a1a51..3e68cb62a 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_selftest.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_selftest.c
@@ -33,7 +33,7 @@
/**
*
* @file xiicps_selftest.c
-* @addtogroup iicps_v3_0
+* @addtogroup iicps_v3_7
* @{
*
* This component contains the implementation of selftest functions for the
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_sinit.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_sinit.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_sinit.c
index 7d7dadaa8..a5724c246 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_sinit.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_sinit.c
@@ -33,7 +33,7 @@
/**
*
* @file xiicps_sinit.c
-* @addtogroup iicps_v3_0
+* @addtogroup iicps_v3_7
* @{
*
* The implementation of the XIicPs component's static initialization
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_slave.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_slave.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_slave.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_slave.c
index fef640b77..fb8919201 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_slave.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_slave.c
@@ -32,7 +32,7 @@
/*****************************************************************************/
/**
* @file xiicps_slave.c
-* @addtogroup iicps_v3_0
+* @addtogroup iicps_v3_7
* @{
*
* Handles slave transfers
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/src/pwm_recorder.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/src/pwm_recorder.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/pwm_recorder.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/pwm_recorder.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.h
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/src/pwm_recorder_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder_selftest.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_recorder_v1_0/src/pwm_recorder_selftest.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder_selftest.c
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/src/pwm_signal_out.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/src/pwm_signal_out.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/pwm_signal_out.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/pwm_signal_out.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.h
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/src/pwm_signal_out_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out_selftest.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/drivers/pwm_signal_out_v1_0/src/pwm_signal_out_selftest.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out_selftest.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c
index 086b9887e..c33322c73 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c
@@ -33,7 +33,7 @@
/**
*
* @file xqspips.c
-* @addtogroup qspips_v3_2
+* @addtogroup qspips_v3_4
* @{
*
* Contains implements the interface functions of the XQspiPs driver.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h
index 671f3f636..139ce4d38 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h
@@ -33,7 +33,7 @@
/**
*
* @file xqspips.h
-* @addtogroup qspips_v3_2
+* @addtogroup qspips_v3_4
* @{
* @details
*
@@ -275,6 +275,12 @@
* to remove compilation warnings. CR# 868893.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
+* ms 04/05/17 Modified Comment lines in functions of qspips
+* examples to recognize it as documentation block
+* and modified filename tag in
+* xqspips_dual_flash_stack_lqspi_example.c to include it in
+* doxygen examples.
+* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
*
* </pre>
*
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c
similarity index 96%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_g.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c
index 6723db11f..34f07519d 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c
index 47cf6d4c9..1817b0780 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c
@@ -33,7 +33,7 @@
/**
*
* @file xqspips_hw.c
-* @addtogroup qspips_v3_2
+* @addtogroup qspips_v3_4
* @{
*
* Contains low level functions, primarily reset related.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h
index 404afed94..96c867ad3 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h
@@ -33,7 +33,7 @@
/**
*
* @file xqspips_hw.h
-* @addtogroup qspips_v3_2
+* @addtogroup qspips_v3_4
* @{
*
* This header file contains the identifiers and basic HW access driver
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_options.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_options.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c
index 911391ccd..1cd43f48c 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_options.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c
@@ -33,7 +33,7 @@
/**
*
* @file xqspips_options.c
-* @addtogroup qspips_v3_2
+* @addtogroup qspips_v3_4
* @{
*
* Contains functions for the configuration of the XQspiPs driver component.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_selftest.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c
index 309b36e2b..4c44cdff2 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_selftest.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c
@@ -33,7 +33,7 @@
/**
*
* @file xqspips_selftest.c
-* @addtogroup qspips_v3_2
+* @addtogroup qspips_v3_4
* @{
*
* This file contains the implementation of selftest function for the QSPI
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_sinit.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c
index be154be99..929ecd832 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_sinit.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c
@@ -33,7 +33,7 @@
/**
*
* @file xqspips_sinit.c
-* @addtogroup qspips_v3_2
+* @addtogroup qspips_v3_4
* @{
*
* The implementation of the XQspiPs component's static initialization
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.c
similarity index 93%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.c
index 8c83a8ad3..f6afc0e5a 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xscugic.c
-* @addtogroup scugic_v3_1
+* @addtogroup scugic_v3_8
* @{
*
* Contains required functions for the XScuGic driver for the Interrupt
@@ -114,6 +114,10 @@
* kvn 02/17/17 Add support for changing GIC CPU master at run time.
* kvn 02/28/17 Make the CpuId as static variable and Added new
* XScugiC_GetCpuId to access CpuId.
+* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
+* XScuGic_InterruptUnmapFromCpu, These API's can be used
+* by applications to unmap specific/all interrupts from
+* target CPU. It fixes CR#992490.
*
* </pre>
*
@@ -836,6 +840,76 @@ void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
}
/****************************************************************************/
/**
+* Unmaps specific SPI interrupt from the target CPU
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Cpu_Id is a CPU number from which the interrupt has to be
+* unmapped
+* @param Int_Id is the IRQ source number to modify
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
+{
+ u32 RegValue;
+ u8 BitPos;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+ /*
+ * Identify bit position corresponding to Int_Id and Cpu_Id,
+ * in interrupt target register and clear it
+ */
+ BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id;
+ RegValue &= (~ ( 1U << BitPos ));
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+ RegValue);
+}
+/****************************************************************************/
+/**
+* Unmaps all SPI interrupts from the target CPU
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Cpu_Id is a CPU number from which the interrupts has to be
+* unmapped
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id)
+{
+ u32 Int_Id;
+ u32 Target_Cpu;
+ u32 LocalCpuID = (1U << Cpu_Id);
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ LocalCpuID |= LocalCpuID << 8U;
+ LocalCpuID |= LocalCpuID << 16U;
+
+ for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U)
+ {
+
+ Target_Cpu = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+ /* Remove LocalCpuID from interrupt target register */
+ Target_Cpu &= (~LocalCpuID);
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
+
+ }
+}
+/****************************************************************************/
+/**
* It checks if the interrupt target register contains all interrupts to be
* targeted for current CPU. If they are programmed to be forwarded to current
* cpu, this API disable all interrupts and disable GIC distributor.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.h
similarity index 92%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.h
index fb6624239..e22ee5bc2 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xscugic.h
-* @addtogroup scugic_v3_1
+* @addtogroup scugic_v3_8
* @{
* @details
*
@@ -166,6 +166,19 @@
* XScugiC_GetCpuId to access CpuId.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
+* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro
+* definitions of scugic in xparameters.h
+* 3.8 mus 07/05/17 Updated scugic.tcl to add support for intrrupts connected
+* through util_reduced_vector IP(OR gate)
+* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
+* the HandlerTable in XScuGic_ConfigTable to 0, it removes
+* the compilation warning in xscugic_g.c. Fix for CR#978736.
+* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical
+* definitions for pl to ps interrupts.Fix for CR#980534
+* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
+* XScuGic_InterruptUnmapFromCpu, These API's can be used
+* by applications to unmap specific/all interrupts from
+* target CPU.
*
* </pre>
*
@@ -331,6 +344,8 @@ void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
u8 Priority, u8 Trigger);
void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id);
void XScuGic_Stop(XScuGic *InstancePtr);
void XScuGic_SetCpuID(u32 CpuCoreId);
u32 XScuGic_GetCpuID(void);
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c
similarity index 92%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_g.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c
index e062f1d1f..528e09902 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@@ -49,7 +49,8 @@ XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] =
{
XPAR_PS7_SCUGIC_0_DEVICE_ID,
XPAR_PS7_SCUGIC_0_BASEADDR,
- XPAR_PS7_SCUGIC_0_DIST_BASEADDR
+ XPAR_PS7_SCUGIC_0_DIST_BASEADDR,
+ {{0}} /**< Initialize the HandlerTable to 0 */
}
};
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.c
similarity index 89%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_hw.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.c
index 80feb4d11..6604e3a55 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_hw.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.c
@@ -33,7 +33,7 @@
/**
*
* @file xscugic_hw.c
-* @addtogroup scugic_v3_1
+* @addtogroup scugic_v3_8
* @{
*
* This file contains low-level driver functions that can be used to access the
@@ -65,6 +65,10 @@
* 3.6 kvn 02/17/17 Add support for changing GIC CPU master at run time.
* kvn 02/28/17 Make the CpuId as static variable and Added new
* XScugiC_GetCpuId to access CpuId.
+* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
+* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
+* API's can be used by applications to unmap specific/all
+* interrupts from target CPU. It fixes CR#992490.
*
* </pre>
*
@@ -571,4 +575,75 @@ void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
}
+
+/****************************************************************************/
+/**
+* Unmaps specific SPI interrupt from the target CPU
+*
+* @param DistBaseAddress is the device base address
+* @param Cpu_Id is a CPU number from which the interrupt has to be
+* unmapped
+* @param Int_Id is the IRQ source number to modify
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id, u32 Int_Id)
+{
+ u32 RegValue;
+ u8 BitPos;
+
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+ /*
+ * Identify bit position corresponding to Int_Id and Cpu_Id,
+ * in interrupt target register and clear it
+ */
+ BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id;
+ RegValue &= (~ ( 1U << BitPos ));
+ XScuGic_WriteReg(DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue);
+}
+
+/****************************************************************************/
+/**
+* Unmaps all SPI interrupts from the target CPU
+*
+* @param DistBaseAddress is the device base address
+* @param Cpu_Id is a CPU number from which the interrupts has to be
+* unmapped
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id)
+{
+ u32 Int_Id;
+ u32 Target_Cpu;
+ u32 LocalCpuID = (1U << Cpu_Id);
+
+ LocalCpuID |= LocalCpuID << 8U;
+ LocalCpuID |= LocalCpuID << 16U;
+
+ for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U)
+ {
+
+ Target_Cpu = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+ /* Remove LocalCpuID from interrupt target register */
+ Target_Cpu &= (~LocalCpuID);
+ XScuGic_WriteReg(DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
+
+ }
+}
/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.h
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.h
index 5eaa633e3..08e65f456 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.h
@@ -33,7 +33,7 @@
/**
*
* @file xscugic_hw.h
-* @addtogroup scugic_v3_1
+* @addtogroup scugic_v3_8
* @{
*
* This header file contains identifiers and HW access functions (or
@@ -72,6 +72,10 @@
* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
+* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
+* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
+* API's can be used by applications to unmap specific/all
+* interrupts from target CPU. It fixes CR#992490.
* </pre>
*
******************************************************************************/
@@ -633,6 +637,10 @@ void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
u8 Priority, u8 Trigger);
void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
u8 *Priority, u8 *Trigger);
+void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_intr.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_intr.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_intr.c
index d05a51c5e..d82a60b9e 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_intr.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_intr.c
@@ -33,7 +33,7 @@
/**
*
* @file xscugic_intr.c
-* @addtogroup scugic_v3_1
+* @addtogroup scugic_v3_8
* @{
*
* This file contains the interrupt processing for the driver for the Xilinx
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_selftest.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_selftest.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_selftest.c
index 47620d644..7b1028f9f 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_selftest.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_selftest.c
@@ -33,7 +33,7 @@
/**
*
* @file xscugic_selftest.c
-* @addtogroup scugic_v3_1
+* @addtogroup scugic_v3_8
* @{
*
* Contains diagnostic self-test functions for the XScuGic driver.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_sinit.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_sinit.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_sinit.c
index d30390ab8..842f31812 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_sinit.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_sinit.c
@@ -33,7 +33,7 @@
/**
*
* @file xscugic_sinit.c
-* @addtogroup scugic_v3_1
+* @addtogroup scugic_v3_8
* @{
*
* Contains static init functions for the XScuGic driver for the Interrupt
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
similarity index 96%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
index 9d81780fc..1634bb77c 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
index 8e9788551..cd9e15d2c 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
@@ -1,4 +1,3 @@
-/* $Id: xscuwdt.c,v 1.1.2.1 2011/01/20 04:04:40 sadanan Exp $ */
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
similarity index 96%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
index ba21a50bf..14fbf75db 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.c
similarity index 88%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.c
index 38b11168a..8b1f11382 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xsdps.c
-* @addtogroup sdps_v2_5
+* @addtogroup sdps_v3_5
* @{
*
* Contains the interface functions of the XSdPs driver.
@@ -78,6 +78,19 @@
* sk 02/01/17 Added HSD and DDR mode support for eMMC.
* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
* sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
+* mn 07/17/17 Add support for running SD at 200MHz
+* mn 07/26/17 Fixed compilation warnings
+* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
+* mn 08/17/17 Added CCI support for A53 and disabled data cache
+* operations when it is enabled.
+* mn 08/22/17 Updated for Word Access System support
+* mn 09/06/17 Resolved compilation errors with IAR toolchain
+* mn 09/26/17 Added UHS_MODE_ENABLE macro to enable UHS mode
+* 3.4 mn 10/17/17 Use different commands for single and multi block
+* transfers
+* mn 03/02/18 Move UHS macro check to SD card initialization routine
+* 3.5 mn 04/18/18 Resolve compilation warnings for sdps driver
* </pre>
*
******************************************************************************/
@@ -94,6 +107,7 @@
#define XSDPS_CMD1_HIGH_VOL 0x00FF8000U
#define XSDPS_CMD1_DUAL_VOL 0x00FF8010U
#define HIGH_SPEED_SUPPORT 0x2U
+#define UHS_SDR50_SUPPORT 0x4U
#define WIDTH_4_BIT_SUPPORT 0x4U
#define SD_CLK_25_MHZ 25000000U
#define SD_CLK_19_MHZ 19000000U
@@ -109,9 +123,7 @@
#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U
#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U
#define CSD_SPEC_VER_3 0x3U
-
-/* Note: Remove this once fixed */
-#define UHS_BROKEN
+#define SCR_SPEC_VER_3 0x80U
/**************************** Type Definitions *******************************/
@@ -123,10 +135,9 @@ s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr);
-#ifndef UHS_BROKEN
static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr);
-#endif
+u16 TransferMode;
/*****************************************************************************/
/**
*
@@ -179,6 +190,7 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
InstancePtr->Config.BankNumber = ConfigPtr->BankNumber;
InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO;
+ InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent;
InstancePtr->SectorCount = 0;
InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
InstancePtr->Config_TapDelay = NULL;
@@ -257,10 +269,18 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
XSDPS_POWER_CTRL_OFFSET,
PowerLevel | XSDPS_PC_BUS_PWR_MASK);
+
+#ifdef __aarch64__
/* Enable ADMA2 in 64bit mode. */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET,
+ XSDPS_HC_DMA_ADMA2_64_MASK);
+#else
+ /* Enable ADMA2 in 32bit mode. */
XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
XSDPS_HOST_CTRL1_OFFSET,
XSDPS_HC_DMA_ADMA2_32_MASK);
+#endif
/* Enable all interrupt status except card interrupt initially */
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
@@ -281,10 +301,8 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
* Transfer mode register - default value
* DMA enabled, block count enabled, data direction card to host(read)
*/
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_XFER_MODE_OFFSET,
- XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
- XSDPS_TM_DAT_DIR_SEL_MASK);
+ TransferMode = XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
+ XSDPS_TM_DAT_DIR_SEL_MASK;
/* Set block size to 512 by default */
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
@@ -335,6 +353,10 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+#ifndef UHS_MODE_ENABLE
+ InstancePtr->Config.BusWidth = XSDPS_WIDTH_4;
+#endif
+
if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
!= XSDPS_CAPS_EMB_SLOT)) {
@@ -402,9 +424,17 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
goto RETURN_PATH;
}
- Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U);
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
- Arg |= XSDPS_OCR_S18;
+ Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U);
+ /*
+ * There is no support to switch to 1.8V and use UHS mode on
+ * 1.0 silicon
+ */
+ if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+ (XGetPSVersion_Info() > XPS_VERSION_1) &&
+#endif
+ (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
+ Arg |= XSDPS_OCR_S18;
}
/* 0x40300000 - Host High Capacity support & 3.3V window */
@@ -426,19 +456,14 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
InstancePtr->HCS = 1U;
}
- /* There is no support to switch to 1.8V and use UHS mode on 1.0 silicon */
-#ifndef UHS_BROKEN
- if (((RespOCR & XSDPS_OCR_S18) != 0U) &&
- (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
+ if ((RespOCR & XSDPS_OCR_S18) != 0U) {
InstancePtr->Switch1v8 = 1U;
Status = XSdPs_Switch_Voltage(InstancePtr);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
-
}
-#endif
/* CMD2 for Card ID */
Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
@@ -536,12 +561,13 @@ s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
{
#ifdef __ICCARM__
#pragma data_alignment = 32
-static u8 ExtCsd[512];
+ static u8 ExtCsd[512];
+ u8 SCR[8] = { 0U };
#pragma data_alignment = 4
#else
-static u8 ExtCsd[512] __attribute__ ((aligned(32)));
+ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
+ u8 SCR[8] __attribute__ ((aligned(32))) = { 0U };
#endif
- u8 SCR[8] = { 0U };
u8 ReadBuff[64] = { 0U };
s32 Status;
u32 Arg;
@@ -649,6 +675,66 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
goto RETURN_PATH;
}
+ if (((SCR[2] & SCR_SPEC_VER_3) != 0U) &&
+ (ReadBuff[13] >= UHS_SDR50_SUPPORT) &&
+ (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) &&
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+ (XGetPSVersion_Info() > XPS_VERSION_1) &&
+#endif
+ (InstancePtr->Switch1v8 == 0U)) {
+ u16 CtrlReg, ClockReg;
+
+ /* Stop the clock */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+ CtrlReg);
+
+ /* Enabling 1.8V in controller */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
+ CtrlReg);
+
+ /* Wait minimum 5mSec */
+ (void)usleep(5000U);
+
+ /* Check for 1.8V signal enable bit is cleared by Host */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Wait for internal clock to stabilize */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ }
+
+ /* Enable SD clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+ /* Wait for 1mSec */
+ (void)usleep(1000U);
+
+ InstancePtr->Switch1v8 = 1U;
+ }
+
#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
if (InstancePtr->Switch1v8 != 0U) {
@@ -895,7 +981,6 @@ RETURN_PATH:
return Status;
}
-#ifndef UHS_BROKEN
/*****************************************************************************/
/**
*
@@ -986,7 +1071,6 @@ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
RETURN_PATH:
return Status;
}
-#endif
/*****************************************************************************/
/**
@@ -1066,8 +1150,8 @@ s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
}
}
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CMD_OFFSET,
- (u16)CommandReg);
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
+ (CommandReg << 16) | TransferMode);
/* Polling for response for now */
do {
@@ -1187,6 +1271,7 @@ u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd)
case CMD24:
case CMD25:
RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+ break;
case ACMD41:
RetVal |= RESP_R3;
break;
@@ -1258,20 +1343,32 @@ s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
}
XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((INTPTR)Buff,
+ BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+ }
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_XFER_MODE_OFFSET,
- XSDPS_TM_AUTO_CMD12_EN_MASK |
- XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
- XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK);
+ if (BlkCnt == 1U) {
+ TransferMode = XSDPS_TM_BLK_CNT_EN_MASK |
+ XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
- Xil_DCacheInvalidateRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+ /* Send single block read command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD17, Arg, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+ TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
+ XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
+ XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK;
- /* Send block read command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
+ /* Send multiple blocks read command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
}
/* Check for transfer complete */
@@ -1349,19 +1446,31 @@ s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
}
XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
- Xil_DCacheFlushRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheFlushRange((INTPTR)Buff,
+ BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+ }
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_XFER_MODE_OFFSET,
- XSDPS_TM_AUTO_CMD12_EN_MASK |
+ if (BlkCnt == 1U) {
+ TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ /* Send single block write command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD24, Arg, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+ TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
XSDPS_TM_BLK_CNT_EN_MASK |
- XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+ XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
- /* Send block write command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
+ /* Send multiple blocks write command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
}
/*
@@ -1463,8 +1572,13 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
}
for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
+#ifdef __aarch64__
+ InstancePtr->Adma2_DescrTbl[DescNum].Address =
+ (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#else
InstancePtr->Adma2_DescrTbl[DescNum].Address =
(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#endif
InstancePtr->Adma2_DescrTbl[DescNum].Attribute =
XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
/* This will write '0' to length field which indicates 65536 */
@@ -1472,8 +1586,13 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
(u16)XSDPS_DESC_MAX_LENGTH;
}
+#ifdef __aarch64__
+ InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
+ (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#else
InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#endif
InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute =
XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
@@ -1481,13 +1600,18 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length =
(u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH));
+#ifdef __aarch64__
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_EXT_OFFSET,
+ (u32)(((u64)&(InstancePtr->Adma2_DescrTbl[0]))>>32));
+#endif
XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
(u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]));
- Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]),
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]),
sizeof(XSdPs_Adma2Descriptor) * 32U);
-
+ }
}
/*****************************************************************************/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xsdps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.h
similarity index 94%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xsdps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.h
index 9e475207d..b8d979d1d 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xsdps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xsdps.h
-* @addtogroup sdps_v2_5
+* @addtogroup sdps_v3_5
* @{
* @details
*
@@ -144,6 +144,11 @@
* sk 02/01/17 Consider bus width parameter from design for switching
* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
* sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
+* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
+* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
+* information.
+* mn 09/06/17 Resolved compilation errors with IAR toolchain
*
* </pre>
*
@@ -161,6 +166,7 @@ extern "C" {
#include "xil_cache.h"
#include "xstatus.h"
#include "xsdps_hw.h"
+#include "xplatform_info.h"
#include <string.h>
/************************** Constant Definitions *****************************/
@@ -184,14 +190,25 @@ typedef struct {
u32 BusWidth; /**< Bus Width */
u32 BankNumber; /**< MIO Bank selection for SD */
u32 HasEMIO; /**< If SD is connected to EMIO */
+ u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
} XSdPs_Config;
/* ADMA2 descriptor table */
typedef struct {
u16 Attribute; /**< Attributes of descriptor */
u16 Length; /**< Length of current dma transfer */
+#ifdef __aarch64__
+ u64 Address; /**< Address of current dma transfer */
+#else
u32 Address; /**< Address of current dma transfer */
+#endif
+#ifdef __ICCARM__
+#pragma data_alignment = 32
} XSdPs_Adma2Descriptor;
+#pragma data_alignment = 4
+#else
+} __attribute__((__packed__))XSdPs_Adma2Descriptor;
+#endif
/**
* The XSdPs driver instance data. The user is required to allocate a
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_g.c
similarity index 94%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_g.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_g.c
index b8eca64ba..4fcd04067 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@@ -54,7 +54,8 @@ XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] =
XPAR_PS7_SD_0_HAS_WP,
XPAR_PS7_SD_0_BUS_WIDTH,
XPAR_PS7_SD_0_MIO_BANK,
- XPAR_PS7_SD_0_HAS_EMIO
+ XPAR_PS7_SD_0_HAS_EMIO,
+ XPAR_PS7_SD_0_IS_CACHE_COHERENT
}
};
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xsdps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_hw.h
similarity index 96%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xsdps_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_hw.h
index 6bb6c2a61..c63d8f62a 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xsdps_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_hw.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xsdps_hw.h
-* @addtogroup sdps_v2_5
+* @addtogroup sdps_v3_5
* @{
*
* This header file contains the identifiers and basic HW access driver
@@ -57,6 +57,10 @@
* operating modes.
* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
* 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 08/22/17 Updated for Word Access System support
+* mn 09/06/17 Added support for ARMCC toolchain
+* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
+*
* </pre>
*
******************************************************************************/
@@ -995,6 +999,13 @@ extern "C" {
#define XSDPS_SD_SDR50_MAX_CLK 100000000U
#define XSDPS_SD_DDR50_MAX_CLK 50000000U
#define XSDPS_SD_SDR104_MAX_CLK 208000000U
+/*
+ * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
+ * than the clock value coming from the core. This value is kept to safely
+ * switch to SDR104 mode if the SD card supports it.
+ */
+#define XSDPS_SD_INPUT_MAX_CLK 175000000U
+
#define XSDPS_MMC_HS200_MAX_CLK 200000000U
#define XSDPS_MMC_HSD_MAX_CLK 52000000U
#define XSDPS_MMC_DDR_MAX_CLK 52000000U
@@ -1163,8 +1174,18 @@ extern "C" {
* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
*
******************************************************************************/
-#define XSdPs_ReadReg16(BaseAddress, RegOffset) \
- XSdPs_In16((BaseAddress) + (RegOffset))
+static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u16)Reg;
+#else
+ return XSdPs_In16((BaseAddress) + (RegOffset));
+#endif
+}
/***************************************************************************/
/**
@@ -1182,8 +1203,20 @@ extern "C" {
* u16 RegisterValue)
*
******************************************************************************/
-#define XSdPs_WriteReg16(BaseAddress, RegOffset, RegisterValue) \
- XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue))
+
+static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
/****************************************************************************/
/**
@@ -1199,9 +1232,18 @@ extern "C" {
* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
*
******************************************************************************/
-#define XSdPs_ReadReg8(BaseAddress, RegOffset) \
- XSdPs_In8((BaseAddress) + (RegOffset))
-
+static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u8)Reg;
+#else
+ return XSdPs_In8((BaseAddress) + (RegOffset));
+#endif
+}
/***************************************************************************/
/**
* Write to a register.
@@ -1218,9 +1260,19 @@ extern "C" {
* u8 RegisterValue)
*
******************************************************************************/
-#define XSdPs_WriteReg8(BaseAddress, RegOffset, RegisterValue) \
- XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue))
-
+static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
/***************************************************************************/
/**
* Macro to get present status register
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_options.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_options.c
similarity index 94%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_options.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_options.c
index 6743f1b34..4894754ad 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_options.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_options.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xsdps_options.c
-* @addtogroup sdps_v2_5
+* @addtogroup sdps_v3_5
* @{
*
* Contains API's for changing the various options in host and card.
@@ -68,6 +68,13 @@
* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
* vns 03/13/17 Fixed MISRAC mandatory violation
* sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 07/25/17 Removed SD0_OTAPDLYENA and SD1_OTAPDLYENA bits
+* mn 08/07/17 Properly set OTAPDLY value by clearing previous bit
+* settings
+* mn 08/17/17 Added CCI support for A53 and disabled data cache
+* operations when it is enabled.
+* mn 08/22/17 Updated for Word Access System support
+* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
*
* </pre>
*
@@ -100,6 +107,7 @@ void XSdPs_SetTapDelay(XSdPs *InstancePtr);
static void XSdPs_DllReset(XSdPs *InstancePtr);
#endif
+extern u16 TransferMode;
/*****************************************************************************/
/**
* Update Block size for read/write operations.
@@ -199,11 +207,11 @@ s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR)
XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_XFER_MODE_OFFSET,
- XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
- Xil_DCacheInvalidateRange((INTPTR)SCR, 8);
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((INTPTR)SCR, 8);
+ }
Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt);
if (Status != XST_SUCCESS) {
@@ -419,13 +427,13 @@ s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_XFER_MODE_OFFSET,
- XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
Arg = XSDPS_SWITCH_CMD_HS_GET;
- Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64);
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64);
+ }
Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
if (Status != XST_SUCCESS) {
@@ -501,11 +509,11 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
- Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+ }
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_XFER_MODE_OFFSET,
- XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
Arg = XSDPS_SWITCH_CMD_HS_SET;
@@ -864,12 +872,11 @@ s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
- Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U);
-
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_XFER_MODE_OFFSET,
- XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U);
+ }
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
/* Send SEND_EXT_CSD command */
Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U);
@@ -991,7 +998,7 @@ void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff)
Xil_AssertVoid(InstancePtr != NULL);
if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) &&
- (InstancePtr->Config.InputClockHz >= XSDPS_MMC_HS200_MAX_CLK)) {
+ (InstancePtr->Config.InputClockHz >= XSDPS_SD_INPUT_MAX_CLK)) {
InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104;
InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
}
@@ -1054,10 +1061,11 @@ s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode)
XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
- Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+ }
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
- XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
switch (Mode) {
case 0U:
@@ -1166,8 +1174,7 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
BlkSize);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
- XSDPS_TM_DAT_DIR_SEL_MASK);
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK;
CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_HOST_CTRL2_OFFSET);
@@ -1256,9 +1263,6 @@ void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
if (DeviceId == 0U) {
#if EL1_NONSECURE && defined (__aarch64__)
(void)TapDelay;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
- ((u64)SD0_OTAPDLYENA << 32), (u64)SD0_OTAPDLYENA,
- 0, 0, 0, 0, 0);
if (Bank == 2)
Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
@@ -1270,8 +1274,7 @@ void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
#else
/* Program the OTAPDLY */
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
- TapDelay |= SD0_OTAPDLYENA;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+ TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
if (Bank == 2)
TapDelay |= SD0_OTAPDLYSEL_HS200_B2;
else
@@ -1283,9 +1286,6 @@ void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
(void) DeviceId;
#if EL1_NONSECURE && defined (__aarch64__)
(void)TapDelay;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
- ((u64)SD1_OTAPDLYENA << 32), (u64)SD1_OTAPDLYENA,
- 0, 0, 0, 0, 0);
if (Bank == 2)
Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
@@ -1296,8 +1296,7 @@ void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
(u64)SD1_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0);
#else
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
- TapDelay |= SD1_OTAPDLYENA;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+ TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
if (Bank == 2)
TapDelay |= SD1_OTAPDLYSEL_HS200_B2;
else
@@ -1332,17 +1331,13 @@ void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
if (DeviceId == 0U) {
#if EL1_NONSECURE && defined (__aarch64__)
(void)TapDelay;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
- ((u64)SD0_OTAPDLYENA << 32), (u64)SD0_OTAPDLYENA,
- 0, 0, 0, 0, 0);
Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
((u64)SD0_OTAPDLY_SEL_MASK << 32), (u64)SD0_OTAPDLYSEL_SD50,
0, 0, 0, 0, 0);
#else
/* Program the OTAPDLY */
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
- TapDelay |= SD0_OTAPDLYENA;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+ TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
TapDelay |= SD0_OTAPDLYSEL_SD50;
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
#endif
@@ -1351,16 +1346,12 @@ void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
(void) DeviceId;
#if EL1_NONSECURE && defined (__aarch64__)
(void)TapDelay;
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
- ((u64)SD1_OTAPDLYENA << 32), (u64)SD1_OTAPDLYENA,
- 0, 0, 0, 0, 0);
Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
((u64)SD1_OTAPDLY_SEL_MASK << 32), (u64)SD1_OTAPDLYSEL_SD50,
0, 0, 0, 0, 0);
#else
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
- TapDelay |= SD1_OTAPDLYENA;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+ TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
TapDelay |= SD1_OTAPDLYSEL_SD50;
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
#endif
@@ -1407,9 +1398,6 @@ void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
(u64)SD0_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
- ((u64)SD0_OTAPDLYENA << 32), (u64)SD0_OTAPDLYENA,
- 0, 0, 0, 0, 0);
if (CardType == XSDPS_CARD_SD)
Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
@@ -1434,8 +1422,7 @@ void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
/* Program the OTAPDLY */
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
- TapDelay |= SD0_OTAPDLYENA;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+ TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
if (CardType == XSDPS_CARD_SD)
TapDelay |= SD0_OTAPDLYSEL_SD_DDR50;
else
@@ -1464,9 +1451,6 @@ void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
SD_ITAPDLY) | ((u64)SD1_ITAPCHGWIN << 32),
(u64)0x0, 0, 0, 0, 0, 0);
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
- SD_OTAPDLY) | ((u64)SD1_OTAPDLYENA << 32), (u64)SD1_OTAPDLYENA,
- 0, 0, 0, 0, 0);
if (CardType == XSDPS_CARD_SD)
Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR +
SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
@@ -1491,8 +1475,7 @@ void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
/* Program the OTAPDLY */
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
- TapDelay |= SD1_OTAPDLYENA;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+ TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
if (CardType == XSDPS_CARD_SD)
TapDelay |= SD1_OTAPDLYSEL_SD_DDR50;
else
@@ -1537,9 +1520,6 @@ void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
0, 0, 0, 0, 0);
Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
- ((u64)SD0_OTAPDLYENA << 32), (u64)SD0_OTAPDLYENA,
- 0, 0, 0, 0, 0);
if (CardType == XSDPS_CARD_SD)
Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
@@ -1561,8 +1541,7 @@ void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
/* Program the OTAPDLY */
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
- TapDelay |= SD0_OTAPDLYENA;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+ TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
if (CardType == XSDPS_CARD_SD)
TapDelay |= SD0_OTAPDLYSEL_SD_HSD;
else
@@ -1585,9 +1564,6 @@ void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
0, 0, 0, 0, 0);
Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
((u64)SD1_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
- Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
- ((u64)SD1_OTAPDLYENA << 32), (u64)SD1_OTAPDLYENA,
- 0, 0, 0, 0, 0);
if (CardType == XSDPS_CARD_SD)
Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
@@ -1609,8 +1585,7 @@ void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
/* Program the OTAPDLY */
TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
- TapDelay |= SD1_OTAPDLYENA;
- XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+ TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
if (CardType == XSDPS_CARD_SD)
TapDelay |= SD1_OTAPDLYSEL_SD_HSD;
else
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_sinit.c
similarity index 97%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_sinit.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_sinit.c
index e0936b308..62bbfc0dd 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_sinit.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_sinit.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xsdps_sinit.c
-* @addtogroup sdps_v2_5
+* @addtogroup sdps_v3_5
* @{
*
* The implementation of the XSdPs component's static initialization
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_exit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_exit.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_exit.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_exit.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_open.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_open.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_open.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_open.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_sbrk.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_sbrk.c
similarity index 95%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_sbrk.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_sbrk.c
index 2a069ec06..967bdfc5b 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_sbrk.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_sbrk.c
@@ -54,15 +54,10 @@ __attribute__((weak)) caddr_t _sbrk ( s32 incr )
}
prev_heap = heap;
+ if (((heap + incr) <= HeapEndPtr) && (prev_heap != NULL)) {
heap += incr;
-
- if (heap > HeapEndPtr){
- Status = (caddr_t) -1;
- }
- else if (prev_heap != NULL) {
Status = (caddr_t) ((void *)prev_heap);
- }
- else {
+ } else {
Status = (caddr_t) -1;
}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/abort.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/abort.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/abort.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/abort.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/asm_vectors.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/asm_vectors.S
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/asm_vectors.S
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/asm_vectors.S
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/boot.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/boot.S
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/boot.S
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/boot.S
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/bspconfig.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/bspconfig.h
similarity index 89%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/bspconfig.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/bspconfig.h
index 87363749e..b977241ce 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/bspconfig.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/bspconfig.h
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@@ -37,4 +37,9 @@
*
*******************************************************************/
+#ifndef BSPCONFIG_H /* prevent circular inclusions */
+#define BSPCONFIG_H /* by using protection macros */
+
#define MICROBLAZE_PVR_NONE
+
+#endif /*end of __BSPCONFIG_H_*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/changelog.txt b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/changelog.txt
similarity index 82%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/changelog.txt
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/changelog.txt
index eb58ff217..0dab3e943 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/changelog.txt
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/changelog.txt
@@ -457,5 +457,93 @@
* HSI command. This change fixes it.
* 6.2 mus 03/22/17 Updated standalone tcl to generate xparameter XPAR_FPD_IS_CACHE_COHERENT, if
* any FPD peripheral is configured to use CCI.It fixes CR#972638
+ * 6.3 mus 03/20/17 Updated cortex-r5 BSP, to add hard floating point support.
+ * 6.3 mus 04/17/17 Updated Cortex-a53 32 bit BSP boot code to fix bug in
+ * the HW coherency enablement. It fixes the CR#973287
+ * 6.3 mus 04/20/17 Updated Cortex-A53 64 bit BSP boot code, to remove redundant write to the
+ * L2CTLR_EL1 register. It fixes the CR#974698
+ * 6.4 mus 06/08/17 Updated arm/common/xil_exception.c to fix warnings in C level exception handlers
+ * of ARM 32 bit processor's.
+ * 6.4 mus 06/14/17 Updated cortexa53/64bit/gcc/asm_vectors.S to fix bug in IRQInterruptHandler code
+ * snippet, which checks for the FPEN bit of CPACR_EL1 register.
+ * 6.4 ms 05/23/17 Added PSU_PMU macro in xplatform_info.c, xparameters.h to support
+ * XGetPSVersion_Info function for PMUFW.
+ * ms 06/13/17 Added PSU_PMU macro in xplatform_info.c to support XGetPlatform_Info
+ * function for PMUFW.
+ * 6.4 mus 07/05/17 Updated Xil_In32BE function in xil_io.h to fix bug.It fixes CR#979740.
+ * 6.4 mus 07/25/17 Updated a53 32 bit boot code and vectors to support hard floating point
+ * operations.Now,VFP is being enabled in FPEXC register, through boot code
+ * and FPU registers are being saved/restored when irq/fiq vector is invoked.
+ * 6.4 adk 08/01/17 Updated standalone tcl to generate xparameter XPAR_PL_IS_CACHE_COHERENT,
+ * if h/w design configured with HPC port.
+ * 6.4 mus 08/10/17 Updated a53 64 bit translation table to mark memory as a outer shareable for
+ * EL1 NS execution. This change has been done to support CCI enabled IP's.
+ * 6.4 mus 08/11/17 Updated a53 64 bit boot code to implement ARM erratum 855873.This fixes
+ * CR#982209.
+ * 6.4 asa 08/16/17 Made several changes in the R5 MPU handling logic. Added new APIs to
+ * make RPU MPU handling user-friendly. This also fixes the CR-981028.
+ * 6.4 mus 08/17/17 Updated XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info APIs to read
+ * version register through SMC call, over EL1 NS mode. This change has been done to
+ * support these APIs over EL1 NS mode.
+ * 6.5 mus 10/20/17 Updated standalone.tcl to fix bug in mb_can_handle_exceptions_in_delay_slots proc,
+ * it fixes CR#987464.
+ * 6.6 mus 12/07/17 Updated cortexa9/xil_errata.h and cortexa9/xil_cache.c to remove Errata 753970.
+ * It fixes CR#989132.
+ * srm 10/18/17 Updated all the sleep routines in a9,a53,R5,microblaze. Now the sleep routines
+ * will use the timer specified by the user to provide delay. A9 and A53 can use
+ * Global timer or TTC. R5 can use TTC or the machine cycles. Microblaze can use
+ * machine cycles or Axi timer. Updated standalone.tcl and standalone.mld files
+ * to support the sleep configuration Added new API's for the Axi timer in
+ * microblaze and TTC in ARM. Added two new files, xil_sleeptimer.c and
+ * xil_sleeptimer.h in ARM for the common sleep routines and 1 new file,
+ * xil_sleepcommon.c in Standalone-common for sleep/usleep API's.
+ * 6.6 hk 12/15/17 Export platform macros to bspconfig.h based on the processor.
+ * 6.6 asa 1/16/18 Ensure C stack information for A9 are flushed out from L1 D cache
+ * or L2 cache only when the respective caches are enabled. This fixes CR-922023.
+ * 6.6 mus 01/19/18 Updated asm_vectors.S and boot.S in Cortexa53 64 bit BSP, to add isb
+ * after writing to cpacr_el1/cptr_el3 registers. It would ensure
+ * disabling/enabling of floating-point unit, before any subsequent
+ * instruction.
+ * 6.6 mus 01/30/18 Updated hypervisor enabled Cortexa53 64 bit BSP, to add xen PV console
+ * support. Now, xil_printf would use PV console instead of UART in case of
+ * hypervisor enabled BSP.
+ * 6.6 mus 02/02/18 Updated get_connected_if proc in standalone tcl to detect the HPC port
+ * configured with smart interconnect.It fixes CR#990318.
+ * 6.6 srm 02/10/18 Updated csu_wdt interrupt to the correct value. Fixes CR#992229
+ * 6.6 asa 02/12/18 Fix for heap handling for ARM platforms. CR#993932.
+ * 6.6 mus 02/19/18 Updated standalone.tcl to fix bug in handle_profile_opbtimer proc,
+ * CR#995014.
+ * 6.6 mus 02/23/18 Presently Cortex R5 BSP boot code is disabling the debug logic in
+* non-JTAG boot mode, when processor is in lockstep configuration.
+* This behavior is restricting application debugging in non-JTAG boot
+* mode. To get rid of this restriction, added new mld parameter
+* "lockstep_mode_debug", to enable/disable debug logic from BSP
+* settings. Now, debug logic can be enabled through BSP settings,
+* by modifying value of parameter "lockstep_mode_debug" as "true".
+* It fixes CR#993896.
+ * 6.6.mus 02/27/18 Updated Xil_DCacheInvalidateRange and
+* Xil_ICacheInvalidateRange APIs in Cortexa53 64 bit BSP, to fix bug
+* in handling upper DDR addresses.It fixes CR#995581.
+* 6.6 mus 03/12/18 Updated makefile of Cortexa53 32bit BSP to add includes_ps directory
+* in the list of include paths. This change allows applications/BSP
+* files to include .h files in include_ps directory.
+* 6.6 mus 03/16/18 By default CPUACTLR_EL1 is accessible only from EL3, it
+* results into abort if accessed from EL1 non secure privilege
+* level. Updated Xil_ConfigureL1Prefetch function in Cortexa53 64 bit BSP
+* to avoid CPUACTLR_EL1 access from privile levels other than EL3.
+* 6.6 mus 03/16/18 Updated hypervisor enabled BSP to use PV console, based on the
+* XEN_USE_PV_CONSOLE flag. By deafault hypervisor enabled BSP would
+* use UART console, PV console can be enabled by appending
+ "-DXEN_USE_PV_CONSOLE" to the BSP extra compiler flags.
*
+* 6.7 mus 04/27/18 Removed __ARM_NEON__ flag definition. Now, saving/restoring of of HW
+* floating point register would be done through newly introduced flag
+* FPU_HARD_FLOAT_ABI_ENABLED. This new flag will be configured based on
+* the -mfpu-abi option in extra compiler flags.. This change has
+* been done to avoid saving/restoring of HW floating point registers,
+* when BSP is not compiled with HW floating point configuration.
+* 6.7 asa 04/26/18 Added API Xil_GetExceptionRegisterHandler for obtaining information
+* on an already registered exception vector.
+* 6.7 asa 05/18/18 Fixed bugss in the API Xil_GetExceptionRegisterHandler.
+*
*****************************************************************************************/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/close.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/close.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/close.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/close.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/config.make b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/config.make
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/config.make
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/config.make
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/cpu_init.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/cpu_init.S
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/cpu_init.S
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/cpu_init.S
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/errno.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/errno.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/errno.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/errno.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/fcntl.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fcntl.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/fcntl.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fcntl.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/fstat.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fstat.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/fstat.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fstat.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/getpid.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/getpid.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/getpid.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/getpid.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/inbyte.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/inbyte.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/inbyte.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/inbyte.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/isatty.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/isatty.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/isatty.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/isatty.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/kill.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/kill.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/kill.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/kill.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/lseek.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/lseek.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/lseek.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/lseek.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/open.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/open.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/open.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/open.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/outbyte.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/outbyte.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/outbyte.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/outbyte.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/print.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/print.c
similarity index 90%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/print.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/print.c
index 74d70ee4a..da7e768d0 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/print.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/print.c
@@ -21,6 +21,9 @@
void print(const char8 *ptr)
{
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+ XPVXenConsole_Write(ptr);
+#else
#ifdef STDOUT_BASEADDRESS
while (*ptr != (char8)0) {
outbyte (*ptr);
@@ -29,4 +32,5 @@ void print(const char8 *ptr)
#else
(void)ptr;
#endif
+#endif
}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_clean.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_clean.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_clean.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_clean.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_init.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_init.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_init.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_init.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_timer_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_timer_hw.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_timer_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_timer_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/dummy.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/dummy.S
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/dummy.S
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/dummy.S
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/mblaze_nt_types.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/mblaze_nt_types.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/mblaze_nt_types.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/mblaze_nt_types.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_cg.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_cg.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_cg.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_cg.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_config.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_config.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_config.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_config.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_hist.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_hist.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_hist.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_hist.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_mcount_arm.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_arm.S
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_mcount_arm.S
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_arm.S
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_mcount_mb.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_mb.S
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_mcount_mb.S
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_mb.S
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_mcount_ppc.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_ppc.S
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_mcount_ppc.S
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_ppc.S
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/putnum.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/putnum.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/putnum.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/putnum.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/read.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/read.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/read.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/read.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sbrk.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sbrk.c
similarity index 94%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sbrk.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sbrk.c
index 64d5156af..87a753d49 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sbrk.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sbrk.c
@@ -51,12 +51,8 @@ __attribute__((weak)) char8 *sbrk (s32 nbytes)
static char8 *heap_ptr = HeapBase;
base = heap_ptr;
- if(heap_ptr != NULL) {
+ if((heap_ptr != NULL) && (heap_ptr + nbytes <= (char8 *)&HeapLimit + 1)) {
heap_ptr += nbytes;
- }
-
-/* if (heap_ptr <= ((char8 *)&_heap_end + 1)) */
- if (heap_ptr <= ((char8 *)&HeapLimit + 1)) {
return base;
} else {
errno = ENOMEM;
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sleep.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.c
similarity index 80%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sleep.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.c
index 039fa61bd..f85743b47 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sleep.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -44,6 +44,10 @@
* 1.00a ecm/sdm 11/11/09 First release
* 3.07a sgd 07/05/12 Updated sleep function to make use Global
* 6.0 asa 08/15/16 Updated the sleep signature. Fix for CR#956899.
+* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
+* implementation. Now sleep routines will use Timer
+* specified by the user (i.e. Global timer/TTC timer)
+*
* </pre>
*
******************************************************************************/
@@ -53,6 +57,10 @@
#include "xtime_l.h"
#include "xparameters.h"
+#if defined (SLEEP_TIMER_BASEADDR)
+#include "xil_sleeptimer.h"
+#endif
+
/*****************************************************************************/
/*
*
@@ -65,16 +73,20 @@
* @note None.
*
****************************************************************************/
-unsigned sleep(unsigned int seconds)
+unsigned sleep_A9(unsigned int seconds)
{
- XTime tEnd, tCur;
+#if defined (SLEEP_TIMER_BASEADDR)
+ Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND);
+#else
+ XTime tEnd, tCur;
- XTime_GetTime(&tCur);
- tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
- do
- {
- XTime_GetTime(&tCur);
- } while (tCur < tEnd);
+ XTime_GetTime(&tCur);
+ tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
+ do
+ {
+ XTime_GetTime(&tCur);
+ } while (tCur < tEnd);
+#endif
return 0;
}
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.h
new file mode 100644
index 000000000..f53b2d8c8
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.h
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file sleep.h
+*
+* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
+* related APIs.
+*
+* <pre>
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 11/02/17 Added processor specific sleep rountines
+* function prototypes.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This macro polls an address periodically until a condition is met or till the
+* timeout occurs.
+* The minimum timeout for calling this macro is 100us. If the timeout is less
+* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
+* If the timeout is not a multiple of 100us, it waits for a timeout of
+* the next usec value which is a multiple of 100us.
+*
+* @param IO_func - accessor function to read the register contents.
+* Depends on the register width.
+* @param ADDR - Address to be polled
+* @param VALUE - variable to read the value
+* @param COND - Condition to checked (usually involves VALUE)
+* @param TIMEOUT_US - timeout in micro seconds
+*
+* @return 0 - when the condition is met
+* -1 - when the condition is not met till the timeout period
+*
+* @note none
+*
+*****************************************************************************/
+#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
+ ( { \
+ u64 timeout = TIMEOUT_US/100; \
+ if(TIMEOUT_US%100!=0) \
+ timeout++; \
+ for(;;) { \
+ VALUE = IO_func(ADDR); \
+ if(COND) \
+ break; \
+ else { \
+ usleep(100); \
+ timeout--; \
+ if(timeout==0) \
+ break; \
+ } \
+ } \
+ (timeout>0) ? 0 : -1; \
+ } )
+
+void usleep(unsigned long useconds);
+void sleep(unsigned int seconds);
+int usleep_R5(unsigned long useconds);
+unsigned sleep_R5(unsigned int seconds);
+int usleep_MB(unsigned long useconds);
+unsigned sleep_MB(unsigned int seconds);
+int usleep_A53(unsigned long useconds);
+unsigned sleep_A53(unsigned int seconds);
+int usleep_A9(unsigned long useconds);
+unsigned sleep_A9(unsigned int seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/smc.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/smc.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/smc.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/smc.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/translation_table.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/translation_table.S
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/translation_table.S
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/translation_table.S
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/unlink.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/unlink.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/unlink.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/unlink.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/usleep.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/usleep.c
similarity index 83%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/usleep.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/usleep.c
index 9171d4382..65eea28cf 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/usleep.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/usleep.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -48,6 +48,9 @@
* possible to generate timer in nanosecond due to
* limited cpu frequency
* 6.0 asa 08/15/16 Updated the usleep signature. Fix for CR#956899.
+* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
+* implementation. Now sleep routines will use Timer
+* specified by the user (i.e. Global timer/TTC timer)
* </pre>
*
******************************************************************************/
@@ -60,8 +63,17 @@
#include "xpseudo_asm.h"
#include "xreg_cortexa9.h"
+#if defined (SLEEP_TIMER_BASEADDR)
+#include "xil_sleeptimer.h"
+#endif
+
+/**************************** Constant Definitions ************************/
+#if defined (SLEEP_TIMER_BASEADDR)
+#define COUNTS_PER_USECOND (SLEEP_TIMER_FREQUENCY / 1000000)
+#else
/* Global Timer is always clocked at half of the CPU frequency */
#define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U))
+#endif
/*****************************************************************************/
/**
@@ -76,8 +88,11 @@
* @note None.
*
****************************************************************************/
-int usleep(unsigned long useconds)
+int usleep_A9(unsigned long useconds)
{
+#if defined (SLEEP_TIMER_BASEADDR)
+ Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND);
+#else
XTime tEnd, tCur;
XTime_GetTime(&tCur);
@@ -86,6 +101,7 @@ int usleep(unsigned long useconds)
{
XTime_GetTime(&tCur);
} while (tCur < tEnd);
+#endif
return 0;
}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/vectors.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/vectors.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/vectors.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/vectors.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/write.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/write.c
similarity index 93%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/write.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/write.c
index aaa879e73..9389f610a 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/write.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/write.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -82,6 +82,14 @@ write (sint32 fd, char8* buf, sint32 nbytes)
__attribute__((weak)) sint32
_write (sint32 fd, char8* buf, sint32 nbytes)
{
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+ sint32 length;
+
+ (void)fd;
+ (void)nbytes;
+ length = XPVXenConsole_Write(buf);
+ return length;
+#else
#ifdef STDOUT_BASEADDRESS
s32 i;
char8* LocalBuf = buf;
@@ -108,5 +116,6 @@ _write (sint32 fd, char8* buf, sint32 nbytes)
(void)nbytes;
return 0;
#endif
+#endif
}
#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xbasic_types.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xbasic_types.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xbasic_types.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xbasic_types.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xdebug.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xdebug.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xdebug.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xdebug.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xenv.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xenv.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xenv_standalone.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv_standalone.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xenv_standalone.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv_standalone.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil-crt0.S b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil-crt0.S
similarity index 91%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil-crt0.S
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil-crt0.S
index 64175fef9..6beb6fd15 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil-crt0.S
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil-crt0.S
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -48,6 +48,9 @@
* initialization of uart smc nor and sram
* 5.3 pkp 10/07/15 Added support for OpenAMP by not initializing global
* timer when USE_AMP flag is defined
+* 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API.
+* Now the TTC instance as specified by the user will be
+* started.
* </pre>
*
* @note
@@ -55,6 +58,7 @@
* None.
*
******************************************************************************/
+#include "bspconfig.h"
.file "xil-crt0.S"
.section ".got2","aw"
@@ -113,6 +117,11 @@ _start:
mov r0, #0x0
mov r1, #0x0
+ /* Reset and start Triple Timer Counter */
+ #if defined SLEEP_TIMER_BASEADDR
+ bl XTime_StartTTCTimer
+ #endif
+
#if USE_AMP != 1
bl XTime_SetTime
#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_assert.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_assert.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_assert.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_assert.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.c
similarity index 97%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.c
index 83f68352f..259c3b1f1 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.c
@@ -92,6 +92,12 @@
* 5.03 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
* application(when USE_AMP flag is defined for BSP) as master CPU
* would be utilizing L2 cache for its operation
+* 6.6 mus 12/07/17 Errata 753970 is not applicable for the PL130 cache controller
+* version r0p2, which is present in zynq. So,removed the handling
+* related to same.It fixes CR#989132.
+* 6.6 asa 16/01/18 Changes made in Xil_L1DCacheInvalidate and Xil_L2CacheInvalidate
+* routines to ensure the stack data flushed only when the respective
+* caches are enabled. This fixes CR-992023.
*
* </pre>
*
@@ -162,11 +168,7 @@ static inline void Xil_L2CacheSync(void)
static void Xil_L2CacheSync(void)
#endif
{
-#ifdef CONFIG_PL310_ERRATA_753970
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET, 0x0U);
-#else
Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U);
-#endif
}
#endif
/****************************************************************************/
@@ -787,6 +789,7 @@ void Xil_L1DCacheInvalidate(void)
#ifdef __GNUC__
u32 stack_start,stack_end,stack_size;
+ register u32 CtrlReg;
#endif
currmask = mfcpsr();
@@ -797,8 +800,15 @@ void Xil_L1DCacheInvalidate(void)
stack_start = (u32)&__undef_stack;
stack_size=stack_start-stack_end;
- /*Flush stack memory to save return address*/
- Xil_DCacheFlushRange(stack_end, stack_size);
+ /* Check for the cache status. If cache is enabled, then only
+ * flush stack memory to save return address. If cache is disabled,
+ * dont flush anything as it might result in flushing stale date into
+ * memory which is undesirable.
+ * */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
+ Xil_DCacheFlushRange(stack_end, stack_size);
+ }
#endif
/* Select cache level 0 and D cache in CSSR */
@@ -1379,12 +1389,22 @@ void Xil_L2CacheInvalidate(void)
{
#ifdef __GNUC__
u32 stack_start,stack_end,stack_size;
+ register u32 L2CCReg;
stack_end = (u32)&_stack_end;
stack_start = (u32)&__undef_stack;
stack_size=stack_start-stack_end;
+ /* Check for the cache status. If cache is enabled, then only
+ * flush stack memory to save return address. If cache is disabled,
+ * dont flush anything as it might result in flushing stale date into
+ * memory which is undesirable.
+ */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+ if ((L2CCReg & 0x01U) != 0U) {
/*Flush stack memory to save return address*/
- Xil_DCacheFlushRange(stack_end, stack_size);
+ Xil_DCacheFlushRange(stack_end, stack_size);
+ }
+
#endif
u32 ResultDCache;
/* Invalidate the caches */
@@ -1618,4 +1638,4 @@ void Xil_L2CacheStoreLine(u32 adr)
/* synchronize the processor */
dsb();
}
-#endif
\ No newline at end of file
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache_l.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_l.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache_l.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_l.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache_vxworks.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_vxworks.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache_vxworks.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_vxworks.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_errata.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_errata.h
similarity index 96%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_errata.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_errata.h
index 800fcd562..490aebeab 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_errata.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_errata.h
@@ -52,6 +52,7 @@
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a srt 04/18/13 First release
+* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
* </pre>
*
******************************************************************************/
@@ -113,15 +114,10 @@
*/
#define CONFIG_PL310_ERRATA_727915 1
-/**
- * Errata No: 753970
- * Description: Cache sync operation may be faulty
- */
-#define CONFIG_PL310_ERRATA_753970 1
/*@}*/
#endif /* ENABLE_ARM_ERRATA */
#endif /* XIL_ERRATA_H */
/**
* @} End of "addtogroup a9_errata".
-*/
\ No newline at end of file
+*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_exception.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.c
similarity index 86%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_exception.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.c
index a1dfdf6eb..d34fd2199 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_exception.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2015 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -46,6 +46,12 @@
* 6.0 mus 27/07/16 Consolidated exceptions for a53,a9 and r5
* processors and added Xil_UndefinedExceptionHandler
* for a53 32 bit and r5 as well.
+* 6.4 mus 08/06/17 Updated debug prints to replace %x with the %lx, to
+* fix the warnings.
+* 6.7 mna 26/04/18 Add an API to obtain a corresponding
+* Xil_ExceptionHandler entry from XExc_VectorTable.
+* 6.7 asa 18/05/18 Fix bugs in the API Xil_GetExceptionRegisterHandler.
+*
* </pre>
*
*****************************************************************************/
@@ -173,6 +179,31 @@ void Xil_ExceptionRegisterHandler(u32 Exception_id,
XExc_VectorTable[Exception_id].Data = Data;
}
+/*****************************************************************************/
+/**
+* @brief Get a handler for a specific exception. This handler is being
+* called when the processor encounters the specified exception.
+*
+* @param exception_id contains the ID of the exception source and should
+* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+* See xil_exception.h for further information.
+* @param Handler to the Handler for that exception.
+* @param Data is a reference to Data that will be passed to the
+* Handler when it gets called.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_GetExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler *Handler,
+ void **Data)
+{
+ *Handler = XExc_VectorTable[Exception_id].Handler;
+ *Data = XExc_VectorTable[Exception_id].Data;
+}
+
/*****************************************************************************/
/**
*
@@ -267,8 +298,8 @@ void Xil_DataAbortHandler(void *CallBackRef){
{ volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
FaultStatus = Reg; }
#endif
- xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %x\n",FaultStatus);
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Data abort %x\n",DataAbortAddr);
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %lx\n",FaultStatus);
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr);
#endif
while(1) {
;
@@ -302,8 +333,8 @@ void Xil_PrefetchAbortHandler(void *CallBackRef){
{ volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
FaultStatus = Reg; }
#endif
- xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %x\n",FaultStatus);
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Prefetch abort %x\n",PrefetchAbortAddr);
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %lx\n",FaultStatus);
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr);
#endif
while(1) {
;
@@ -324,7 +355,7 @@ void Xil_PrefetchAbortHandler(void *CallBackRef){
****************************************************************************/
void Xil_UndefinedExceptionHandler(void *CallBackRef){
(void) CallBackRef;
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %x\n",UndefinedExceptionAddr);
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %lx\n",UndefinedExceptionAddr);
while(1) {
;
}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_exception.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.h
similarity index 97%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_exception.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.h
index ad4822205..83303875d 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_exception.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.h
@@ -51,6 +51,8 @@
* ----- -------- -------- -----------------------------------------------
* 5.2 pkp 28/05/15 First release
* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
+* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
+* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
* </pre>
*
******************************************************************************/
@@ -235,6 +237,8 @@ extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
void *Data);
extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler *Handler, void **Data);
extern void Xil_ExceptionInit(void);
#if defined (__aarch64__)
@@ -253,4 +257,4 @@ extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
#endif /* XIL_EXCEPTION_H */
/**
* @} End of "addtogroup arm_exception_apis".
-*/
\ No newline at end of file
+*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_hal.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_hal.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_hal.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_hal.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_io.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_io.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_io.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_io.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.h
index 99bf4d05d..9c5aa43c7 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_io.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.h
@@ -303,7 +303,7 @@ static INLINE u32 Xil_In32LE(UINTPTR Addr)
static INLINE u32 Xil_In32BE(UINTPTR Addr)
#endif
{
- u16 value = Xil_In32(Addr);
+ u32 value = Xil_In32(Addr);
return Xil_EndianSwap32(value);
}
@@ -342,4 +342,4 @@ static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_io_interfacing_apis".
-*/
\ No newline at end of file
+*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_macroback.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_macroback.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_macroback.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_macroback.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mem.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mem.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mem.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mem.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_misc_psreset_api.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_misc_psreset_api.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_misc_psreset_api.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_misc_psreset_api.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mmu.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mmu.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mmu.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mmu.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_printf.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.c
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_printf.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.c
index 9dffed148..dc0897f0d 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_printf.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.c
@@ -75,8 +75,8 @@ static void outs(const charptr lp, struct params_s *par)
(par->num2)--;
#ifdef STDOUT_BASEADDRESS
outbyte(*LocalPtr);
- LocalPtr += 1;
#endif
+ LocalPtr += 1;
}
/* Pad on right if needed */
@@ -135,8 +135,8 @@ static void outnum( const s32 n, const s32 base, struct params_s *par)
while (&outbuf[i] >= outbuf) {
#ifdef STDOUT_BASEADDRESS
outbyte( outbuf[i] );
- i--;
#endif
+ i--;
}
padding( par->left_flag, par);
}
@@ -239,6 +239,11 @@ static s32 getnum( charptr* linep)
/* void esp_printf( const func_ptr f_ptr,
const charptr ctrl1, ...) */
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+void xil_printf( const char8 *ctrl1, ...){
+ XPVXenConsole_Printf(ctrl1);
+}
+#else
void xil_printf( const char8 *ctrl1, ...)
{
s32 Check;
@@ -262,8 +267,8 @@ void xil_printf( const char8 *ctrl1, ...)
if (*ctrl != '%') {
#ifdef STDOUT_BASEADDRESS
outbyte(*ctrl);
- ctrl += 1;
#endif
+ ctrl += 1;
continue;
}
@@ -434,5 +439,5 @@ void xil_printf( const char8 *ctrl1, ...)
}
va_end( argp);
}
-
+#endif
/*---------------------------------------------------*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_printf.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.h
similarity index 91%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_printf.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.h
index 2be5c5734..016ae3b2f 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_printf.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.h
@@ -10,6 +10,10 @@ extern "C" {
#include <stdarg.h>
#include "xil_types.h"
#include "xparameters.h"
+#include "bspconfig.h"
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+#include "xen_console.h"
+#endif
/*----------------------------------------------------*/
/* Use the following parameter passing structure to */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleepcommon.c
similarity index 56%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_sinit.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleepcommon.c
index ef3c6ea6b..972a310a8 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_sinit.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleepcommon.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -32,67 +32,75 @@
/*****************************************************************************/
/**
*
-* @file xttcps_sinit.c
-* @addtogroup ttcps_v3_0
-* @{
+*@file xil_sleepcommon.c
*
-* The implementation of the XTtcPs driver's static initialization functionality.
+* This file contains the sleep API's
*
* <pre>
* MODIFICATION HISTORY:
*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------
-* 1.00a drg/jz 01/21/10 First release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.6 srm 11/02/17 First release
* </pre>
-*
******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xttcps.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "sleep.h"
-/************************** Function Prototypes ******************************/
+/**************************** Constant Definitions *************************/
-/************************** Variable Definitions *****************************/
-extern XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES];
/*****************************************************************************/
/**
*
-* Looks up the device configuration based on the unique device ID. A table
-* contains the configuration info for each device in the system.
+* This API gives delay in sec
*
-* @param DeviceId contains the unique ID of the device
+* @param seconds - delay time in seconds
*
-* @return
+* @return none
*
-* A pointer to the configuration found or NULL if the specified device ID was
-* not found. See xttcps.h for the definition of XTtcPs_Config.
+* @note none
*
-* @note None.
-*
-******************************************************************************/
-XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId)
-{
- XTtcPs_Config *CfgPtr = NULL;
- u32 Index;
+*****************************************************************************/
+ void sleep(unsigned int seconds)
+ {
+#if defined (ARMR5)
+ sleep_R5(seconds);
+#elif defined (__aarch64__) || defined (ARMA53_32)
+ sleep_A53(seconds);
+#elif defined (__MICROBLAZE__)
+ sleep_MB(seconds);
+#else
+ sleep_A9(seconds);
+#endif
- for (Index = 0U; Index < (u32)XPAR_XTTCPS_NUM_INSTANCES; Index++) {
- if (XTtcPs_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XTtcPs_ConfigTable[Index];
- break;
- }
- }
+ }
+
+/****************************************************************************/
+/**
+*
+* This API gives delay in usec
+*
+* @param useconds - delay time in useconds
+*
+* @return none
+*
+* @note none
+*
+*****************************************************************************/
+ void usleep(unsigned long useconds)
+ {
+#if defined (ARMR5)
+ usleep_R5(useconds);
+#elif defined (__aarch64__) || defined (ARMA53_32)
+ usleep_A53(useconds);
+#elif defined (__MICROBLAZE__)
+ usleep_MB(useconds);
+#else
+ usleep_A9(useconds);
+#endif
- return (XTtcPs_Config *)CfgPtr;
-}
-/** @} */
+ }
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.c
new file mode 100644
index 000000000..5bf30ccb4
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.c
@@ -0,0 +1,162 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.c
+*
+* This file provides the common helper routines for the sleep API's
+*
+* <pre>
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 10/18/17 First Release.
+* 6.6 srm 04/20/18 Fixed compilation warning in Xil_SleepTTCCommon API
+*
+* </pre>
+*****************************************************************************/
+
+/**************************** Include Files ********************************/
+
+#include "xil_io.h"
+#include "xil_sleeptimer.h"
+#include "xtime_l.h"
+
+/**************************** Constant Definitions *************************/
+
+
+/* Function definitions are applicable only when TTC3 is present*/
+#if defined (SLEEP_TIMER_BASEADDR)
+/****************************************************************************/
+/**
+*
+* This is a helper function used by sleep/usleep APIs to
+* have delay in sec/usec
+*
+* @param delay - delay time in seconds/micro seconds
+*
+* @param frequency - Number of counts per second/micro second
+*
+* @return none
+*
+* @note none
+*
+*****************************************************************************/
+void Xil_SleepTTCCommon(u32 delay, u64 frequency)
+{
+ u64 tEnd = 0U;
+ u64 tCur = 0U;
+ XCntrVal TimeHighVal = 0U;
+ XCntrVal TimeLowVal1 = 0U;
+ XCntrVal TimeLowVal2 = 0U;
+
+ TimeLowVal1 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
+ tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency);
+ do
+ {
+ TimeLowVal2 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
+ if (TimeLowVal2 < TimeLowVal1) {
+ TimeHighVal++;
+ }
+ TimeLowVal1 = TimeLowVal2;
+ tCur = (((u64) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) |
+ (u64)TimeLowVal2;
+ }while (tCur < tEnd);
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This API starts the Triple Timer Counter
+*
+* @param none
+*
+* @return none
+*
+* @note none
+*
+*****************************************************************************/
+void XTime_StartTTCTimer()
+{
+ u32 TimerPrescalar;
+ u32 TimerCntrl;
+
+#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32)
+ u32 LpdRst;
+
+ LpdRst = XSleep_ReadCounterVal(RST_LPD_IOU2);
+
+ /* check if the timer is reset */
+ if (((LpdRst & (RST_LPD_IOU2_TTC_BASE_RESET_MASK <<
+ XSLEEP_TTC_INSTANCE)) != 0 )) {
+ LpdRst = LpdRst & (~(RST_LPD_IOU2_TTC_BASE_RESET_MASK <<
+ XSLEEP_TTC_INSTANCE));
+ Xil_Out32(RST_LPD_IOU2, LpdRst);
+ } else {
+#endif
+ TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
+ /* check if Timer is disabled */
+ if ((TimerCntrl & XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK) == 0) {
+ TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
+ /* check if Timer is configured with proper functionalty for sleep */
+ if ((TimerPrescalar & XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK) == 0)
+ return;
+ }
+#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32)
+ }
+#endif
+ /* Disable the timer to configure */
+ TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
+ TimerCntrl = TimerCntrl | XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK;
+ Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
+ TimerCntrl);
+ /* Disable the prescalar */
+ TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
+ TimerPrescalar = TimerPrescalar & (~XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK);
+ Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET,
+ TimerPrescalar);
+ /* Enable the Timer */
+ TimerCntrl = TimerCntrl & (~XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK);
+ Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
+ TimerCntrl);
+}
+#endif
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.h
new file mode 100644
index 000000000..4bfac0ac4
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.h
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
+* For sleep related functions that can be used across all Xilinx supported
+* processors, please use xil_sleeptimer.h.
+*
+*
+* <pre>
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 10/18/17 First Release.
+*
+* </pre>
+*****************************************************************************/
+
+#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */
+#define XIL_SLEEPTIMER_H /* by using protection macros */
+/**************************** Include Files ********************************/
+
+#include "xil_io.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+
+/************************** Constant Definitions *****************************/
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#define XSLEEP_TIMER_REG_SHIFT 32U
+#define XSleep_ReadCounterVal Xil_In32
+#define XCntrVal u32
+#else
+#define XSLEEP_TIMER_REG_SHIFT 16U
+#define XSleep_ReadCounterVal Xil_In16
+#define XCntrVal u16
+#endif
+
+#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
+#define RST_LPD_IOU2 0xFF5E0238U
+#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U
+#endif
+
+#if defined (SLEEP_TIMER_BASEADDR)
+/** @name Register Map
+*
+* Register offsets from the base address of the TTC device
+*
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U
+ /**< Clock Control Register */
+ #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU
+ /**< Counter Control Register*/
+ #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U
+ /**< Current Counter Value */
+/* @} */
+/** @name Clock Control Register
+* Clock Control Register definitions of TTC
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U
+ /**< Prescale enable */
+/* @} */
+/** @name Counter Control Register
+* Counter Control Register definitions of TTC
+* @{
+*/
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U
+ /**< Disable the counter */
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U
+ /**< Reset counter */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SleepTTCCommon(u32 delay, u64 frequency);
+void XTime_StartTTCTimer();
+
+#endif
+#endif /* XIL_SLEEPTIMER_H */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testcache.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testcache.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testcache.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testcache.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testio.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testio.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testio.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testio.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testmem.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testmem.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testmem.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testmem.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_types.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_types.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_types.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_types.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc_counter.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc_counter.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc_counter.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc_counter.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xparameters_ps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xparameters_ps.h
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xparameters_ps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xparameters_ps.h
index ea0d2bcde..0fa77710d 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xparameters_ps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xparameters_ps.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -45,6 +45,8 @@
* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
* driver tcl
* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
+* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
+*
* </pre>
*
* @note
@@ -60,6 +62,9 @@
extern "C" {
#endif
+/**************************** Include Files *******************************/
+
+
/************************** Constant Definitions *****************************/
/*
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xplatform_info.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.c
similarity index 77%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xplatform_info.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.c
index d196ceaa7..2c08e5f2e 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xplatform_info.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.c
@@ -45,6 +45,13 @@
* 5.04 pkp 01/12/16 Added platform information support for Cortex-A53 32bit
* mode
* 6.00 mus 17/08/16 Removed unused variable from XGetPlatform_Info
+* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+* function for PMUFW.
+* ms 06/13/17 Added PSU_PMU macro to provide support of
+* XGetPlatform_Info function for PMUFW.
+* mus 08/17/17 Add EL1 NS mode support for
+* XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info
+* APIs.
* </pre>
*
******************************************************************************/
@@ -54,7 +61,10 @@
#include "xil_types.h"
#include "xil_io.h"
#include "xplatform_info.h"
-
+#if defined (__aarch64__)
+#include "bspconfig.h"
+#include "xil_smc.h"
+#endif
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
@@ -79,7 +89,7 @@
u32 XGetPlatform_Info()
{
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
return XPLAT_ZYNQ_ULTRA_MP;
#elif (__microblaze__)
return XPLAT_MICROBLAZE;
@@ -102,9 +112,20 @@ u32 XGetPlatform_Info()
#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
u32 XGet_Zynq_UltraMp_Platform_info()
{
+#if EL1_NONSECURE
+ XSmc_OutVar reg;
+ /*
+ * This SMC call will return,
+ * idcode - upper 32 bits of reg.Arg0
+ * version - lower 32 bits of reg.Arg1
+ */
+ reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+ return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK);
+#else
u32 reg;
reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK);
return reg;
+#endif
}
#endif
@@ -118,12 +139,23 @@ u32 XGet_Zynq_UltraMp_Platform_info()
* @return The information about PS Silicon version.
*
******************************************************************************/
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
u32 XGetPSVersion_Info()
{
+#if EL1_NONSECURE
+ /*
+ * This SMC call will return,
+ * idcode - upper 32 bits of reg.Arg0
+ * version - lower 32 bits of reg.Arg1
+ */
+ XSmc_OutVar reg;
+ reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+ return (u32)(reg.Arg1 & XPS_VERSION_INFO_MASK);
+#else
u32 reg;
reg = (Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET)
& XPS_VERSION_INFO_MASK);
return reg;
+#endif
}
#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xplatform_info.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.h
similarity index 88%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xplatform_info.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.h
index 27c0b5851..0582222bc 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xplatform_info.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -41,6 +41,15 @@
* platform information.
*
* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- --------- -------------------------------------------------------
+* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+* function for PMUFW.
+* </pre>
+*
******************************************************************************/
#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
@@ -70,6 +79,7 @@ extern "C" {
#define XPS_VERSION_2 0x1
#define XPLAT_INFO_MASK (0xF)
+#define XPLAT_INFO_SHIFT (0xC)
#define XPS_VERSION_INFO_MASK (0xF)
/**************************** Type Definitions *******************************/
@@ -79,7 +89,7 @@ extern "C" {
u32 XGetPlatform_Info();
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
u32 XGetPSVersion_Info();
#endif
@@ -96,4 +106,4 @@ u32 XGet_Zynq_UltraMp_Platform_info();
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_platform_info".
-*/
\ No newline at end of file
+*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpm_counter.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpm_counter.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpm_counter.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpm_counter.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpseudo_asm.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpseudo_asm.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xpseudo_asm_gcc.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm_gcc.h
similarity index 96%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm_gcc.h
index 1b6726394..37971bc59 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm_gcc.h
@@ -120,6 +120,13 @@ extern "C" {
rval;\
})
+#define mfelrel3() ({u64 rval = 0U; \
+ asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v))
+
#else
/* pseudo assembler instructions */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xreg_cortexa9.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xreg_cortexa9.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xreg_cortexa9.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xreg_cortexa9.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xstatus.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xstatus.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xstatus.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xstatus.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xtime_l.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xtime_l.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xtime_l.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.h
similarity index 90%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xtime_l.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.h
index f939d84f6..9b872b6cb 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xtime_l.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -48,6 +48,8 @@
* 3.06a sgd 05/15/12 Upadted get/set time functions to make use Global Timer
* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer
+* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
+* implementation
* </pre>
*
******************************************************************************/
@@ -76,9 +78,16 @@ typedef u64 XTime;
#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
#define GTIMER_CONTROL_OFFSET 0x08U
-
+#if defined (SLEEP_TIMER_BASEADDR)
+#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
+#else
/* Global Timer is always clocked at half of the CPU frequency */
#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
+#endif
+
+#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
+#pragma message ("For the sleep routines, Global timer is being used")
+#endif
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.c
index 1a2c708ba..c33ec5481 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.c
@@ -33,7 +33,7 @@
/**
*
* @file xuartps.c
-* @addtogroup uartps_v3_1
+* @addtogroup uartps_v3_5
* @{
*
* This file contains the implementation of the interface functions for XUartPs
@@ -49,6 +49,7 @@
* baud rate. CR# 804281.
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+* 3.5 NK 09/26/17 Fix the RX Buffer Overflow issue.
* </pre>
*
*****************************************************************************/
@@ -463,7 +464,7 @@ u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
* Loop until there is no more data in RX FIFO or the specified
* number of bytes has been received
*/
- while((ReceivedCount <= InstancePtr->ReceiveBuffer.RemainingBytes)&&
+ while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&&
(((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){
if (InstancePtr->is_rxbs_error) {
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.h
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.h
index a5155940e..33758c23b 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xuartps.h
-* @addtogroup uartps_v3_1
+* @addtogroup uartps_v3_5
* @{
* @details
*
@@ -168,6 +168,8 @@
* for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
+* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem
+* control register.
*
* </pre>
*
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c
similarity index 97%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_g.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c
index b76d00b2a..ed841e0ba 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_hw.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.c
index 299dd35ae..724c3cb40 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_hw.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.c
@@ -33,7 +33,7 @@
/**
*
* @file xuartps_hw.c
-* @addtogroup uartps_v3_1
+* @addtogroup uartps_v3_5
* @{
*
*
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xuartps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.h
similarity index 98%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xuartps_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.h
index 9f5f0b700..9a2bc4305 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xuartps_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
/**
*
* @file xuartps_hw.h
-* @addtogroup uartps_v3_1
+* @addtogroup uartps_v3_5
* @{
*
* This header file contains the hardware interface of an XUartPs device.
@@ -55,6 +55,8 @@
* constant definitions.
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+* 3.6 ms 02/16/18 Updates flow control mode offset value in
+* modem control register.
*
* </pre>
*
@@ -256,7 +258,7 @@ extern "C" {
*
* @{
*/
-#define XUARTPS_MODEMCR_FCM 0x00000010U /**< Flow control mode */
+#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
/* @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_intr.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_intr.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_intr.c
index 3068ee795..dff02fd63 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_intr.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_intr.c
@@ -33,7 +33,7 @@
/**
*
* @file xuartps_intr.c
-* @addtogroup uartps_v3_1
+* @addtogroup uartps_v3_5
* @{
*
* This file contains the functions for interrupt handling
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_options.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_options.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_options.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_options.c
index 9a699afa1..5d8d3017c 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_options.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_options.c
@@ -33,7 +33,7 @@
/**
*
* @file xuartps_options.c
-* @addtogroup uartps_v3_1
+* @addtogroup uartps_v3_5
* @{
*
* The implementation of the options functions for the XUartPs driver.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_selftest.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_selftest.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_selftest.c
index a1a7dd366..de58201a1 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_selftest.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_selftest.c
@@ -33,7 +33,7 @@
/**
*
* @file xuartps_selftest.c
-* @addtogroup uartps_v3_1
+* @addtogroup uartps_v3_5
* @{
*
* This file contains the self-test functions for the XUartPs driver.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_sinit.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_sinit.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_sinit.c
index 8dc87dae3..22e2f7a83 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_sinit.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_sinit.c
@@ -33,7 +33,7 @@
/**
*
* @file xuartps_sinit.c
-* @addtogroup uartps_v3_1
+* @addtogroup uartps_v3_5
* @{
*
* The implementation of the XUartPs driver's static initialzation
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c
index 897c09497..b76c94a46 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c
@@ -32,7 +32,7 @@
/******************************************************************************/
/**
* @file xusbps.c
-* @addtogroup usbps_v2_2
+* @addtogroup usbps_v2_4
* @{
*
* The XUsbPs driver. Functions in this file are the minimum required
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h
index 4a4492cdc..b5c472ef9 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h
@@ -33,7 +33,7 @@
/**
*
* @file xusbps.h
-* @addtogroup usbps_v2_2
+* @addtogroup usbps_v2_4
* @{
* @details
*
@@ -185,6 +185,8 @@
* 2.4 sg 04/26/16 Fixed CR#949693, Corrected the logic for EP flush
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
+ * ms 04/10/17 Modified filename tag to include the file in doxygen
+ * examples.
* </pre>
*
******************************************************************************/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c
index f93c4b800..7b16d22b5 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c
@@ -32,7 +32,7 @@
/******************************************************************************/
/**
* @file xusbps_endpoint.c
-* @addtogroup usbps_v2_2
+* @addtogroup usbps_v2_4
* @{
*
* Endpoint specific function implementations.
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps_endpoint.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps_endpoint.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h
index b8b9ad685..1cb0cfcd3 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps_endpoint.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h
@@ -33,7 +33,7 @@
/**
*
* @file xusbps_endpoint.h
-* @addtogroup usbps_v2_2
+* @addtogroup usbps_v2_4
* @{
*
* This is an internal file containung the definitions for endpoints. It is
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
similarity index 96%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
index 79b2959ca..947f86f29 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c
index 105ad9321..04963b288 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c
@@ -33,7 +33,7 @@
/**
*
* @file xusbps_hw.c
-* @addtogroup usbps_v2_2
+* @addtogroup usbps_v2_4
* @{
*
* The implementation of the XUsbPs interface reset functionality
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h
index 792fbdde5..69f3ebffb 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h
@@ -33,7 +33,7 @@
/**
*
* @file xusbps_hw.h
-* @addtogroup usbps_v2_2
+* @addtogroup usbps_v2_4
* @{
*
* This header file contains identifiers and low-level driver functions (or
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c
index 94fd3dee6..83463bdfe 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c
@@ -32,7 +32,7 @@
/******************************************************************************/
/**
* @file xusbps_intr.c
-* @addtogroup usbps_v2_2
+* @addtogroup usbps_v2_4
* @{
*
* This file contains the functions that are related to interrupt processing
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c
index 1da441db5..a2070a76e 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c
@@ -33,7 +33,7 @@
/**
*
* @file xusbps_sinit.c
-* @addtogroup usbps_v2_2
+* @addtogroup usbps_v2_4
* @{
*
* The implementation of the XUsbPs driver's static initialzation
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/Makefile b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/Makefile
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/Makefile
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/Makefile
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xadcps.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h
similarity index 99%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xadcps.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h
index 9b6737d37..549bfff29 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xadcps.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h
@@ -176,7 +176,9 @@
* for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
-*
+* ms 04/05/17 Modified Comment lines in functions of xadcps
+* examples to recognize it as documentation block
+* for doxygen generation.
*
* </pre>
*
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
similarity index 96%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
index 09c6b9d06..157bd00bd 100644
--- a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_intr.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_intr.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_intr.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_intr.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c
similarity index 100%
rename from quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c
rename to quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c
diff --git a/quad/xsdk_workspace_vivado/system_bsp/system.mss b/quad/xsdk_workspace_vivado/system_bsp/system.mss
index 5f6ae5d99..6a49ec106 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/system.mss
+++ b/quad/xsdk_workspace_vivado/system_bsp/system.mss
@@ -4,7 +4,7 @@
BEGIN OS
PARAMETER OS_NAME = standalone
- PARAMETER OS_VER = 6.2
+ PARAMETER OS_VER = 6.7
PARAMETER PROC_INSTANCE = ps7_cortexa9_0
PARAMETER stdin = ps7_uart_0
PARAMETER stdout = ps7_uart_0
@@ -13,7 +13,7 @@ END
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu_cortexa9
- PARAMETER DRIVER_VER = 2.4
+ PARAMETER DRIVER_VER = 2.6
PARAMETER HW_INSTANCE = ps7_cortexa9_0
END
@@ -30,6 +30,18 @@ BEGIN DRIVER
PARAMETER HW_INSTANCE = axi_gpio_1
END
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 4.3
+ PARAMETER HW_INSTANCE = axi_gpio_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 4.3
+ PARAMETER HW_INSTANCE = axi_gpio_3
+END
+
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
@@ -74,7 +86,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = devcfg
- PARAMETER DRIVER_VER = 3.4
+ PARAMETER DRIVER_VER = 3.5
PARAMETER HW_INSTANCE = ps7_dev_cfg_0
END
@@ -92,7 +104,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = emacps
- PARAMETER DRIVER_VER = 3.4
+ PARAMETER DRIVER_VER = 3.7
PARAMETER HW_INSTANCE = ps7_ethernet_0
END
@@ -104,7 +116,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpiops
- PARAMETER DRIVER_VER = 3.2
+ PARAMETER DRIVER_VER = 3.3
PARAMETER HW_INSTANCE = ps7_gpio_0
END
@@ -116,13 +128,13 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 3.5
+ PARAMETER DRIVER_VER = 3.7
PARAMETER HW_INSTANCE = ps7_i2c_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 3.5
+ PARAMETER DRIVER_VER = 3.7
PARAMETER HW_INSTANCE = ps7_i2c_1
END
@@ -164,7 +176,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = qspips
- PARAMETER DRIVER_VER = 3.3
+ PARAMETER DRIVER_VER = 3.4
PARAMETER HW_INSTANCE = ps7_qspi_0
END
@@ -194,7 +206,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = scugic
- PARAMETER DRIVER_VER = 3.6
+ PARAMETER DRIVER_VER = 3.9
PARAMETER HW_INSTANCE = ps7_scugic_0
END
@@ -212,7 +224,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = sdps
- PARAMETER DRIVER_VER = 3.2
+ PARAMETER DRIVER_VER = 3.5
PARAMETER HW_INSTANCE = ps7_sd_0
END
@@ -222,21 +234,15 @@ BEGIN DRIVER
PARAMETER HW_INSTANCE = ps7_slcr_0
END
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.3
- PARAMETER HW_INSTANCE = ps7_ttc_0
-END
-
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 3.4
+ PARAMETER DRIVER_VER = 3.6
PARAMETER HW_INSTANCE = ps7_uart_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 3.4
+ PARAMETER DRIVER_VER = 3.6
PARAMETER HW_INSTANCE = ps7_uart_1
END
--
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